Stats Chippac Pte. Ltd.

TaeKeun Lee

Youngcheol Kim

Yongmin Kim

Youngmin Kim

Rajendra D Pendse

TaeWoo Kang

YoRim Lee

GuiChea Na

GwangJin Kim

KyungOe Kim

Wagno Alves Braganca, Jr

Hyunil Bae

A semiconductor device has a semiconductor die, substrate, and plurality of first conductive pillars formed over the semiconductor die or substrate. Alternatively, the first conductive pillars formed over the semiconductor die and substrate. An electrical component is disposed over the semiconductor die. The electrical component can be a double-sided IPD. The semiconductor die and electrical component are disposed over the substrate. A shielding frame is disposed over the semiconductor die. A plurality of second conductive pillars is formed over a first surface of the electrical component. A plurality of third conductive pillars is formed over a second surface of the electrical component opposite the first surface of the electrical component. A bump cap can be formed over a distal end of the conductive pillars. The substrate has a cavity and the electrical component is disposed within the cavity. An underfill material is deposited between the semiconductor die and substrate.

Semiconductor device and method of forming package with double-sided integrated passive device

A semiconductor device has an electrical component and a first TIM with a first compliant property is disposed over a surface of the electrical component. A second TIM having a second compliant property greater than the first compliant property is disposed over the surface of the electrical component within the first TIM. A third TIM can be disposed over the surface of the electrical component along the first TIM. A heat sink is disposed over the first TIM and second TIM. The second TIM has a shape of a star pattern, grid of dots, parallel lines, serpentine, or concentric geometric shapes. The first TIM provides adhesion for joint reliability and the second TIM provides stress relief. Alternatively, a heat spreader is disposed over the first TIM and second TIM and a heat sink is disposed over a third TIM and fourth TIM on the heat spreader.

Semiconductor device and method of forming hybrid TIM layers

A method of making a semiconductor device involves the steps of disposing a first semiconductor die over a substrate and disposing a beam homogenizer over the first semiconductor die. A beam from the beam homogenizer impacts the first semiconductor die. The method further includes the steps of determining a positional offset of the beam relative to the first semiconductor die in a number of pixels, using a first calibration equation to convert the number of pixels into a distance in millimeters, and moving the beam homogenizer the distance in millimeters to align the beam and first semiconductor die.

Die-beam alignment for laser-assisted bonding

A semiconductor device has a substrate and a first semiconductor die disposed over the substrate. A subpackage is also disposed over the substrate. A stiffener is disposed over the substrate around the first semiconductor die and subpackage. A heat spreader is disposed over the stiffener. The heat spreader is thermally coupled to the first semiconductor die. The heat spreader has an opening over the subpackage.

Package with windowed heat spreader

A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed to metallurgically and electrically connect to the contact pads. Each contact pad is sized according to a design rule defined by SRO+2*SRR&#x2212;2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The value of X ranges from 5 to 20 microns. The solder bump wets the exposed sidewall of the contact pad and substantially fills an area adjacent to the exposed sidewall. The contact pad can be made circular, rectangular, or donut-shaped.

Filp chip interconnection structure with bump on partial pad and method thereof

A semiconductor device is made by disposing a film layer over a substrate having first conductive layer. An opening is formed in the film layer to expose the first conductive layer. A second conductive layer is formed over the first conductive layer. A first bump is formed over the second conductive layer which promotes reflow of the first bump at a eutectic temperature. A standoff bump is formed on the film layer around a perimeter of the substrate. The film layer prevents reflow of the standoff bump at the eutectic temperature. A second bump is disposed between a semiconductor die and the first bump. The second bump is reflowed to electrically connect the semiconductor die to the first bump. After reflow of the second bump, the standoff bump has a height at least 70% of the second bump prior to reflow to maintain separation between the semiconductor die and substrate.

Standoff height improvement for bumping technology using solder resist

Flip chip interconnection structure with bump on partial pad and method thereof

A system to support a die includes a substrate. A solder resist is disposed over the substrate. A first solder bump is disposed in the solder resist to provide electrical connectivity through the solder resist to the substrate. A second solder bump is formed over the solder resist to correspond with a peripheral edge or a corner of the die. The second solder bump provides standoff height physical support to the die.

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Kyungki-do, South Korea

TaeKeun Lee