Samsung Electronics Co., Ltd.

Taek-Sung Kim

Kwang-Ho Kim

Woo-Yeong Cho

Kwang-Jin Lee

Hyun-Ho Choi

Yong-Jun Lee

Qi Wang

Hye-Jin Kim

Dongjin Lee

Kwangho Kim

Young-Goo Ko

Hyuck-Sun Kwon

Janghwan Kim

Hwan-Jin Yong

Donghyun Song

Byungse So

Kyoungsub Oh

Byungjin Ahn

Wonseok Lee

Min-Ho Kim

Hye Jin Kim

Jong-Soo Seo

Kwangjin Lee

Min-ho Kim

Wooyeong Cho

Youngkug Moon

Hyunho Choi

Kwan-Jong Park

Tae-Hwa Yoo

Sangbo Lee

Jong-gyu Park

Jonggyu Park

Taehwa Yoo

SoonYong Hur

Kwanjong Park

Jongsoo Seo

A user device is provided. The device includes a main power supply, and an auxiliary power supply. The main power supply provides a main power. The auxiliary power supply cuts off the main power according to a power level of the main power supply and provides an auxiliary power upon Sudden Power-Off (SPO).

Auxiliary power supply and user device including the same

A semiconductor package includes first and second slave chips stacked vertically; and a master chip connected to the first and second slave chips, each of the slave chips including, a plurality of memory blocks, and a redundancy block, and the master chip including, a fuse block configured to repair a defective memory block detected from the first slave chip and a defective memory block detected from the second slave chip by using the redundancy block of the first slave chip and the redundancy block of the second slave chip, respectively, and a block selection circuit configured to, connect the redundancy blocks of the first and second slave chips, one or more non-defective ones of the plurality of memory blocks of the first slave chip, and one or more non-defective ones of the plurality of memory blocks of the second slave chip to an input/output circuit.

Semiconductor package including stacked chips and method of fabricating the same

A method is provided for controlling a write operation in a nonvolatile memory device to provide wear leveling, where the nonvolatile memory device includes multiple memory blocks. The method includes reading write indication information with respect to at least a selected memory block of the multiple memory blocks; determining whether a write order of data to be stored in the selected memory block is an ascending order or a descending order, based on the write indication information of the selected memory block; and generating addresses of memory regions in the selected memory block in an ascending order when the write order of the data is determined to be an ascending order, and generating addresses of the memory regions in the selected memory block in a descending order when the write order is determined to be a descending order.

Nonvolatile memory device having wear-leveling control and method of operating the same

In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.

Semiconductor device having resistance based memory array and method of operation associated therewith

Semiconductor device having resistance based memory array, method of operation, and systems associated therewith

Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.

Variable resistance memory device and system

A semiconductor memory device includes a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.

Growing community of inventors

Yongin-si, South Korea

Taek-Sung Kim