Samsung Electronics Co., Ltd.

Taek Kyun Shin

Jung Hun Heo

Jun Ho Seo

San Ha Kim

Jin Su Park

Min Su Kim

Jae Young Lee

Kwang Ho Kim

Hyun Woo Park

Jae Gon Lee

Woo Sung Lee

Sang Woo Han

Ho Yeon Jeon

Dong Keun Kim

Bong Il Park

Hee Seok Lee

Myung Kyoon Yim

Yun Hyeok Im

Boo-Jin Kim

Cha Jea Jo

Seung Hyun Choi

Yung Hei Lee

Soong Hyun Shin

Je Myoung Ko

Myoung Seok Kong

Jang Ho Cho

An application processor and a system on chip (SoC) that incorporates the application processor are provided. The application processor includes a first core configured to process first data per unit time, a second core configured to process second data larger than the first data per unit time, and a lookup table configured to determine whether to activate the first core or the second core based on at least one of an analysis result of a message signal received by a communications processor, a sensing signal supplied to the application processor and a power level supplied to the communications processor.

Application processor that performs core switching based on modem data and a system on chip (SOC) that incorporates the application processor

Application processor that performs core switching based on modem data and a system on chip (SoC) that incorporates the application processor

A semiconductor device includes a scan input circuit, a master latch, a slave latch, a first inverter, and a scan output circuit. The scan input circuit is configured to receive a scan input signal, a first data signal, and a scan enable signal and select any one of the first data signal and the scan input signal in response to the scan enable signal to output a first select signal. The master latch is configured to latch the first select signal and output a first output signal. The slave latch is configured to latch the first output signal and output a second output signal. The first inverter is configured to invert the second output signal. The scan output circuit is configured to receive a signal output from the slave latch and an external signal and output a first scan output signal.

Semiconductor device

A semiconductor device package and a semiconductor apparatus are provided. The semiconductor device includes a first semiconductor package, a second semiconductor package, and an interposer between the first and second semiconductor packages. The first semiconductor package includes a first semiconductor package substrate and a first semiconductor chip. The second semiconductor package includes a second semiconductor package substrate and a second semiconductor chip. The interposer electrically connects the first semiconductor package to the second semiconductor package and includes a first interposer hole passing through the interposer. The first semiconductor chip includes a second portion which protrudes from a first portion, and the second portion is inserted into the first interposer hole.

Semiconductor device package and apparatus comprising the same

A semiconductor device and a semiconductor system are provided. A semiconductor device includes a monitoring circuit receiving a first operating voltage and a second operating voltage, which is different from the first operating voltage, from a Power Management Integrated Circuit (PMIC) and monitoring a duration of use of a System-on-Chip (SoC) at each of the first and second operating voltages; a processing circuit calculating a normalized value based on predetermined weight information from the duration of use of the SoC at each of the first and second operating voltages; and a voltage circuit determining whether to increase an operating voltage of the SoC by comparing the normalized value with a predetermined value.

Semiconductor device and semiconductor system

A low-power synchronizer circuit, a data processing circuit that incorporates the synchronizer circuit, and a synchronization method are provided. The synchronizer circuit includes a delay circuit for receiving and delaying an asynchronous input signal, a first flip-flop having an input terminal connected to an output terminal of the delay circuit, a clock terminal for receiving the asynchronous input signal, and a reset terminal for receiving the asynchronous input signal, a synchronizer connected to an output terminal of the first flip-flop, and a clock-gating circuit for receiving a clock signal and determining whether to supply the clock signal to the synchronizer in response to one of a first output value of the delay circuit and a second output value of the first flip-flop and a third output value of the synchronizer.

Low-power clock-gated synchronizer, a data processing system that incorporates the same and a synchronization method

A method for operating a system on chip includes receiving an acceleration request signal generated upon execution of an application program, in response to receipt of the acceleration request signal, comparing a current usage of a central processing unit (CPU) with a threshold value to generate a comparison signal, and performing switching between heterogeneous accelerators to accelerate a function executed by the application program in response to the comparison signal.

Data processing system and method for switching between heterogeneous accelerators

A contactless user-interface (UI) motion recognizing device and method of controlling the same are provided. The method includes: obtaining a left-eye image and a right-eye image; determining an object position of an object in the obtained left-eye image and the obtained right-eye image; determining an object brightness of the object; determining depth information of the object using the determined object brightness; determining a three-dimensional (3D) object position of the object using the determined object position and the determined depth information; determining an object moving velocity based on the determined 3D object position and a previous 3D object position; and determining a UI pattern based on the determined 3D object position and the determined object moving velocity, and executing an operation according to the determined UI pattern.

Method of recognizing contactless user interface motion and system there-of

Disclosed is an integrated circuit device including a plurality of power domain blocks, which includes a core power domain block. A power control circuit is configured to control power supplied to each of the plurality of power domain blocks independently responsive to control communication from the core power domain block. The power control circuit includes a plurality of power clusters corresponding to the plurality of power domain blocks, respectively. The plurality of power clusters control power supplied to the plurality of power domain blocks, respectively, independently responsive to the control communication from the core power domain block.

System on chip, devices having the same, and method for power control of the SOC

Growing community of inventors

Gwangmyeong-si, South Korea

Taek Kyun Shin