Samsung Electronics Co., Ltd.

Taek Jung Kim

Do Hyung Kim

Eun Young Lee

Young-Soo Park

Siyoung Choi

Yong Hoon Son

Byeong Chan Lee

Seung Jong Park

Jae Wha Park

Youn Jae Cho

In Soo Jung

Deok Hyung Lee

Eun-Ok Lee

Hyun Su Kim

Igor Shcherbatko

Sun Yong Hwang

Ji Won Yu

Hyo Jung Noh

Jun-Youn Kim

Su-Hee Chae

Jae-Chul Park

Moon-Seung Yang

Hyung-Su Jeong

Bok-Ki Min

A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate including an element isolation film and an active region defined by the element isolation film; a word line crossing the active region in a first direction; and a bit line structure on the substrate and connected to the active region, the bit line structure extending in a second direction crossing the first direction, wherein the bit line structure includes a first cell interconnection film including an amorphous material or ruthenium, a second cell interconnection film on and extending along the first cell interconnection film and including ruthenium, and a cell capping film on and extending along the second cell interconnection film.

Semiconductor device

Semiconductor device and method of fabricating the same

A deposition equipment is provided. The deposition equipment includes: a reaction chamber including an upper plate and a container body, the upper plate including a gas supplier for injecting a processing gas; a wafer chuck including an upper surface on which a wafer is loaded, in the reaction chamber, with the upper surface of the wafer chuck facing the upper plate; and a processing gas shielding section which prevents the processing gas from being adsorbed to the upper surface of the wafer chuck and is disposed between the upper plate and the wafer chuck in a state in which the wafer is removed from the wafer chuck. The processing gas shielding section includes a shutter which is plate-like, and the shutter includes a region including a gas discharge section for jetting a purging gas toward the wafer chuck.

Deposition equipment and method of fabricating semiconductor device using the same

Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produce a wider base portion. The disclosed semiconductor fin construction will also typically include a horizontal step region at the interface between the upper region and the lower region. Also disclosed are a series of methods of manufacturing semiconductor devices incorporating semiconductor fins having this dual construction and incorporating various combinations of insulating materials such as silicon dioxide and/or silicon nitride for forming shallow trench isolation (STI) structures between adjacent semiconductor fins.

Multi-structured Si-fin and method of manufacture

Multi-structured Si-fin

Growing community of inventors

Kyunggi-do, South Korea

Taek Jung Kim