Samsung Electronics Co., Ltd.

Taejun Jeon

Yongkwan Lee

Junwoo Park

Jungjoo Kim

Jongwan Kim

Seunghwan Kim

Hyunggil Baek

Kyonghwan Koh

Seung Hwan Kim

Hyunki Kim

Junga Lee

Junhyeung Jo

Dongju Jang

A semiconductor package including a dielectric layer on a substrate and having an opening that partially exposes a top surface of the substrate, a capacitor chip on the substrate and in the opening of the dielectric layer, connection terminals between the substrate and the capacitor chip and connecting the substrate and the capacitor chip to each other, dielectric patches on the substrate and in the opening of the dielectric layer, and an under-fill filling a space between the substrate and the capacitor chip may be provided. The space between the substrate and the capacitor chip includes a first region, a second region, and a third region between the first and second regions. The connection terminals are on the first region and the second region. The dielectric patches are on the third region.

Semiconductor package

A semiconductor package includes; a package substrate, a semiconductor chip on the package substrate, an electromagnetic shield structure on the package substrate and including an upper cover covering an upper surface of the semiconductor chip and a side cover surrounding the semiconductor chip, and a sealing member contacting the semiconductor chip and the electromagnetic shield structure, wherein the side cover includes first through holes and the upper cover includes second through holes.

Semiconductor package including electromagnetic shield structure

A method of manufacturing a semiconductor package may include providing a substrate having first and second cutting regions respectively provided along first and second side portions opposite to each other and a mounting region between the first and second cutting regions is provided, disposing at least one semiconductor chip on the mounting region, forming a molding member on the substrate, and removing a dummy curl portion and at least portions of dummy runner portions from the molding member. The molding member may include a sealing portion, the dummy curl portion provided outside the second side portion of the substrate, and the plurality of dummy runner portions on the second cutting region to connect the sealing portion and the dummy curl portion. The substrate may include adhesion reducing pads in the second cutting region, which may contact the dummy runner portions respectively.

Molded product for semiconductor strip and method of manufacturing semiconductor package

A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.

Semiconductor package having package substrate

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Suwon-si, South Korea

Taejun Jeon