Samsung Electronics Co., Ltd.

Samsung Electro-mechanics Co., Ltd.

Georgia Tech Research Corporation

Taejoong Song

Sanghoon Baek

Jung-Ho Do

Jinyoung Lim

Jonghoon Jung

Seungyoung Lee

Giyoung Yang

Ha-Young Kim

Jae-Ho Park

Sang-Kyu Oh

Jungho Do

Jisu Yu

Sungwe Cho

Hoon Bae Kim

Tae-Hyung Kim

Dong-Wook Seo

Sang-Yeop Baeck

Jae-Seung Choi

Inhak Lee

Daeyoung Moon

Hyunsu Choi

Jung-Myung Kang

Sun-Yung Jang

Chang-Ho Lee

Suk-Soo Pyo

Woojin Rim

Hyuntaek Jung

Kwangok Jeong

Seolun Yang

Sunyoung Park

Joy Laskar

Haksun Kim

Boyoung Seo

Dalhee Lee

Keunho Lee

Hyosig Won

Gyuhong Kim

Kyutae Lim

Hyoung-Suk Oh

Jeongsuk Lee

Kihong Kim

Jongmin Park

Seongsoo Lee

Yongho Kim

Minjae Jeong

Jintae Kim

Youngsik Hur

Jongsun Park

Woong Il Choi

Wangmyong Woo

Kwanyoung Chun

Seong Ook Jung

Minsik Ahn

Hyeongyu You

Moo-Gyu Bae

Hanwool Jeong

Jeongwon Cha

Hoonki Kim

Changho Han

Jae Joon Chang

Changhyuk Cho

Changnam Park

An integrated circuit may include a first function cell and a second function cell each corresponding to a first circuit, wherein the first function cell may include a first pattern extending in a first direction along a first grid in a first layer and a second pattern extending in the first direction along a second grid in a second layer, the first grid may have a first pitch greater than a second pitch of the second grid in a second direction crossing the first direction, and the second function cell may include a layout of the first function cell and have a length greater than a length of the first function cell by the first pitch in the second direction.

Integrated circuit including standard cells and method of designing the same

A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.

Methods of designing a layout of a semiconductor device including field effect transistor and methods of manufacturing a semiconductor device using the same

A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

Semiconductor device for selectively performing isolation function and layout displacement method thereof

A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

Semiconductor device

A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active fins that protrude from the substrate, the first and second active fins extending in a second direction intersecting the first direction and being spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active fins, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active fin of the first logic cell from the first active fin of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.

Flip-flop including 3-state inverter

A nonvolatile memory device includes a first variable resistance element connected to a first bit line, and a first transmission ;ate connected between the first variable resistance element and a first source line. The first transmission gate includes a first insulating layer formed on a well connected to aground voltage, a first n-channel metal oxide semiconductor (NMOS) transistor formed on the first insulating layer and connected to a first word line, a second insulating layer formed on the well, the second insulating layer being in the same layer as the first insulating layer, and a first p-channel metal oxide semiconductor (PMOS) transistor formed on the second insulating layer and connected to a first write word line.

Nonvolatile memory device and operating method thereof

A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.

Semiconductor device including a gate electrode and a conductive structure

A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active patterns that extend in a second direction intersecting the first direction and that are spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active patterns, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active pattern of the first logic cell from the first active pattern of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

Layout of semiconductor device for selectively operating as insulating circuit or driving circuit

A memory device includes a delay locked loop that generates a first code for delaying a reference clock in a first operation mode that is a normal operation mode, generates a second code for delaying the reference clock in a second operation mode that is a refresh mode, and delays the reference clock in response to one of the first and second codes depending on one of the first and second operation modes, and a data output circuit that outputs a data strobe signal (DQS) using the delayed reference clock.

Nonvolatile memory device and operating method of nonvolatile memory device

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Seongnam-si, South Korea

Taejoong Song