Samsung Electronics Co., Ltd.

Sungkyunkwan University

Research & Business Foundation Sungyunkwan University

Taejin Park

Yoosang Hwang

Sunghee Han

Sohyun Park

Keunnam Kim

Bong-Soo Kim

Chulkwon Park

Hyeonjin Shin

Kyung-Eun Byun

Daeik Kim

Jemin Park

Hyoungsub Kim

Inkyoung Heo

Wonsik Ahn

Mirine Leem

Hoijoon Kim

Wooyoung Choi

Hyo-Sub Kim

Jin-Hwan Chun

Kyujin Kim

Taehoon Kim

Kiseok Lee

Hui-Jung Kim

Yeonchoo Cho

Minho Kim

Eun Ah Kim

Dongjun Lee

Huijung Kim

Hyojong Kim

Dongheon Shin

Daehyoun Kim

Sangho Lee

Daewon Kim

Minwoo Lee

Chihyun Cho

Dongin Kim

Seung-Heon Lee

Jangeun Lee

Donghan Lee

Jongah Kim

Jiyong Kim

Hoondo Heo

Heewoong Yoon

Jeongho Cho

Dongoh Kim

Donghwy Kim

Gwangho Choi

Kihyuk Lee

Kyung-Eun Kim

Kyusung Kim

Ki-Hyung Nam

Youn-seok Choi

Dongsun Lee

Jaehwan Cho

Gilyoung Noh

Soyeong Kim

Hyosun Kim

Jaehun Lim

Heekeun Park

A semiconductor memory device including a substrate including an active pattern that includes a first source/drain region and a second source/drain region; an insulating layer on the substrate; a line structure on the insulating layer and extending in a first direction to cross the active pattern, the line structure penetrating the insulating layer on the first source/drain region and including a bit line electrically connected to the first source/drain region; and a contact spaced apart from the line structure and electrically connected to the second source/drain region, wherein the bit line includes a first portion vertically overlapped with the first source/drain region; and a second portion vertically overlapped with the insulating layer, and wherein a lowermost level of a top surface of the first portion of the bit line is at a level lower than a lowermost level of a top surface of the second portion of the bit line.

Semiconductor memory device

A gate structure may include a first gate electrode extending in a first direction, a second gate electrode on a portion of the first gate electrode, a gate mask on the first and second gate electrodes, and a gate insulation pattern on a lower surface and a sidewall of the first gate electrode and sidewalls of the second gate electrode and the gate mask. The gate structure is in an upper portion of a substrate. A grain size of the second gate electrode is greater than a grain size of the first gate electrode.

Gate structures and semiconductor devices including the same

Provided are a metal chalcogenide thin film and a method and device for manufacturing the same. The metal chalcogenide thin film includes a transition metal element and a chalcogen element, and at least one of the transition metal element and the chalcogen element having a composition gradient along the surface of the metal chalcogenide thin film, the composition gradient being an in-plane composition gradient. The metal chalcogenide thin film may be prepared by using a manufacturing method including providing a transition metal precursor and a chalcogen precursor on a substrate by using a confined reaction space in such a manner that at least one of the transition metal precursor and the chalcogen precursor forms a concentration gradient according to a position on the surface of the substrate; and heat-treating the substrate.

Metal chalcogenide film and method and device for manufacturing the same

An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

Method of forming an integrated circuit devices having buried word lines

An electronic device configured to configure brightness of a display by using an illuminance sensor is provided. The electronic device includes acquiring a second front-surface sensing value smaller than a first front-surface sensing value through a first illuminance sensor while the brightness is a first brightness, comparing the second front-surface sensing value with a first rear-surface sensing value detected through a second illuminance sensor, determining, when the second front-surface sensing value is greater than the first rear-surface sensing value, whether a touch input is detected through a designated region of the display, maintaining the brightness at the first brightness when the touch input is detected, and when the touch input is not detected, adjusting the brightness of the display to a value lower than that of the first brightness, based on a first LUT stored in a memory, or maintaining the brightness of the display at the first brightness.

Electronic device for configuring brightness of display by using illuminance sensor

Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

Semiconductor devices and methods of forming semiconductor devices

A semiconductor memory device includes active regions including first impurity regions and second impurity regions, word lines on the active regions and extended in a first direction, bit lines on the word lines and extended in a second direction crossing the first direction, the bit lines being connected to the first impurity regions, first contact plugs between the bit lines, the first contact plugs being connected to the second impurity regions, landing pads on the first contact plugs, respectively, and gap-fill structures filling spaces between the landing pads, top surfaces of the gap-fill structures being higher than top surfaces of the landing pads.

Semiconductor memory device and method of fabricating the same

The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

Semiconductor devices having improved electrical characteristics and methods of fabricating the same

An electronic device according to an embodiment may include a display, a touch sensor, an illuminance sensor configured to generate illuminance information, a memory configured to store brightness data relating the ambient illuminance to brightness of the display, and a processor. The processor may be configured to identify the illuminance information from the illuminance sensor, configure the brightness of the display as first brightness, based on the illuminance information and the brightness data, change the brightness of the display to second brightness, based on a user input, acquire event information for an operation in which the brightness of the display is changed by the user input, reconfigure the brightness data stored in the memory, based on the event information, and determine the brightness of the display according to a brightness value mapped in the reconfigured brightness data to the illuminance information identified by the illuminance sensor.

Electronic device and method to automatically control the brightness of electronic device

Integrated circuit devices having buried word lines therein

A semiconductor memory device includes a substrate comprising a memory cell region and a dummy cell region surrounding the memory cell region, the memory cell region including a plurality of memory cells, a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width in a short axis direction orthogonal to the long axis direction, and a plurality of dummy active regions in the dummy cell region, each extending in the long axis direction, each of the plurality of dummy active regions having a second width greater than the first width in the short axis direction.

Semiconductor memory devices

A method of forming a transition metal dichalcogenide thin film on a substrate includes treating the substrate with a metal organic material and providing a transition metal precursor and a chalcogen precursor around the substrate to synthesize transition metal dichalcogenide on the substrate. The transition metal precursor may include a transition metal element and the chalcogen precursor may include a chalcogen element.

Method of forming transition metal dichalcogenide thin film

A hardmask structure including a plurality of hardmask layers is formed on a target layer in a first area and a second area, a first photoresist pattern in the first area and a second photoresist pattern in the second area are formed, a reversible hardmask pattern including a plurality of openings is formed by transferring shapes of the first and second photoresist patterns to a reversible hardmask layer that is one of the plurality of hardmask layers, a gap-fill hardmask pattern is formed by filling some of the plurality of openings formed in the first area with a gap-fill hardmask pattern material, and a feature pattern is formed in the target layer by transferring a shape of the gap-fill hardmask pattern to the target layer in the first area and a shape of the reversible hardmask pattern to the target layer in the second area.

Method of forming patterns, integrated circuit device, and method of manufacturing the integrated circuit device

A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.

Semiconductor memory device having spacer capping pattern disposed between burried dielectic pattern and an air gap and method of fabricating same

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Yongin-si, South Korea

Taejin Park