Texas Instruments Corporation

Taehyun Jeon

Brett Anthony McClellan

Leo Fu

Michael Leung

Younggyun Kim

Ming-Tak Leung

Leo Ki-Chun Fu

A Viterbi detector includes circuitry for receiving an NRZ encoded received signal in an EEPR4 channel to decode the signal according to &lgr; &equals;(z &minus;y ) &minus;&agr; , wherein &agr; is m &agr;, &agr; is a positive constant, m is a number of transitions within the most current four symbol periods, &lgr; is a branch metric at time k for an i Viterbi branch, k is a time period, z is a received value at time k, &lgr; is a metric used to determine a next state of the Viterbi based upon a maximum likelihood evaluation for an i branch, a , a , a , a are received state values at respective time periods k, k&minus;1, k&minus;2, and k&minus;3, and y is an ideal sample associated with an i branch. The detector is operated to decode a received data value by determining whether the received value is in a space containing first ( ) and second ( ) possible decode values. The space has a boundary ( ) substantially equidistant from the first ( ) and second ( ) possible decode values and separating the first and second possible decode values. If the received value is within a first portion of the space closest to the first decode value, the received value is decoded as the first decode value. If the received value is within a second portion of the space closest to the second decode value, it is decoded as the second decode value. A value (&agr;) that estimates an amount of jitter noise in a channel ( ) through which the received value has passed is produced. The boundary ( ) is then moved an additive amount (1&agr;, 2&agr;, 3&agr;) determined by the value that estimates an amount of jitter noise, wherein the boundary is moved ( ) to enlarge whichever of the first and second spaces that contains a larger amount of jitter noise.

Modified viterbi detector for jitter noise dominant channels

A circuit for inserting a parity signal into a data stream, including a precoder circuit to precode the data stream to be written on a medium by generating a precoded data stream; a parity circuit to generate a parity signal based on said data stream at a predetermined time; and an insertion circuit to insert said parity signal into said precoded data stream.

Parity insertion with precoder feedback in a read channel

Parity insertion with precoder feedback in a PRML read channel

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Sunnyvale, CA, United States of America

Taehyun Jeon