Samsung Electronics Co., Ltd.

Taehong Min

Chan Soo Hwang

Katsutoshi Sasaki

Woojin Jung

Joonsoo Park

Byeongsoo Kim

Takayuki Sasaoka

Heejung Kim

Cheolhong Kim

Osamu Konuma

Chorong Park

Joohee Seo

Sang-Ho Yun

Un Jeon

Eunsuk Hwang

A method of fabricating a three-dimensional semiconductor memory device includes forming a cell stack layer covering key and cell regions of a substrate and including a variable resistance layer and a switching layer, forming key mask patterns on the cell stack layer of the key region and cell mask patterns on the cell stack layer of the cell region, and simultaneously forming a plurality of key patterns on the key region and a plurality of memory cells on the cell region by etching the cell stack layer using the key and cell mask patterns as an etching mask. Each memory cell includes a variable resistance pattern and a switching pattern formed by etching the variable resistance layer and the switching layer. Each key pattern includes a dummy variable resistance pattern and a dummy switching pattern formed by etching the variable resistance layer and the switching layer.

Method of fabricating three-dimensional semiconductor memory device

Provided are a light source device, a light emission control method, and a computer program for mitigating flickers. The light source device includes a plurality of light sources, and a controller configured to individually control the plurality of light sources to emit light. The controller controls one or more of the plurality of light sources to emit light at random in a time domain or controls such that light emission timings of the plurality of light sources do not overlap.

Light source device and light emission control method

A method of fabricating a semiconductor device includes providing a substrate including a first region and a second region. The method includes forming a first layer on the substrate. The first layer has a first hole on the first region and a second hole on the second region. The method includes forming a second layer in the first hole and the second hole. The method includes forming a mask pattern on the second region of the substrate. The method includes polishing the second layer to form a pattern in the first hole and an overlay key pattern in the second hole. A top surface of the overlay key pattern is further from the substrate than a top surface of the pattern in the first hole.

Method of fabricating a semiconductor device with an overlay key pattern

Provided are methods of generating and revising overlay correction data, a method of performing a photolithography process using the overlay correction data, and a method of performing a photolithography process while revising the overlay correction data. The method of revising the overlay correction data includes forming a plurality of overlay keys on a first set of wafers using first overlay correction data, measuring first overlay keys formed on first overlay coordinates in a first shot area of a first wafer among the first set of wafers, generating first overlay error data, and revising primarily the first overlay correction data using the first overlay error data, measuring second overlay keys formed on second overlay coordinates in a second shot area of a second wafer among the first set of wafers, generating second overlay error data, and revising secondarily the primarily revised first overlay correction data using the second overlay error data, and measuring third overlay keys formed on third overlay coordinates in a third shot area of a third wafer among the first set of wafers, generating third overlay error data, revising tertiarily the secondarily revised first overlay correction data, and generating second overlay correction data. The first overlay coordinates, the second overlay coordinates, and the third overlay coordinates are mutually exclusive.

Methods of revising overlay correction data

Growing community of inventors

Hwaseong-si, South Korea

Taehong Min