Agere Systems Inc.

Lucent Technologies Inc.

Triquint Semiconductor Corporation

At&t Bell Laboratories

Qorvo Us, Inc.

Agere Systems Guardian Corp.

Taeho Kook

Sailesh Mansinh Merchant

Daniel Patrick Chesire

Kurt George Steiner

Seung Hyuk Kang

Benjamin P Abbott

Robert Aigner

Sailesh Chittipeddi

Alan Sangone Chen

Avinoam Kornblit

Julien Gratier

Vance D Archer, Iii

Vivian Wanda Ryan

Mark Adam Bachman

Warren K Gladden

Vance Dolvan Archer

Marc Solal

Kouros Azimi

Tanya Nigam

Chong-Cheng Fu

Bonnie E Weir

Joze E Antol

Philip William Seitzer

Timothy Daniel

Tungsheng Yang

Rafe Carl Mengel

Thomas B Gans

Pradip Kumar Roy

Kuo-Hua Lee

Alvaro Maury

Natalya F Naumenko

Min-Liang Chen

Steven Alan Lytle

Larry Bruce Fritzinger

Robert L Kostelak, Jr

John J DeMarco

Donald Stephen Bitting

Jean Briot

Suzanne Combe

Kolawole R Olasupo

Michael C Ayukawa

Juli H Eisenberg

Larry B Fritzinger

Stephen A Neston

Thomas Michael Wolf

Richard A Powell

Wan Yee Cheung

Scott Shive

Acoustic filtering circuitry includes a piezoelectric layer, a dielectric layer, a plurality of acoustic resonators, and a capacitor. The dielectric layer is over a surface of the piezoelectric layer. The plurality of acoustic resonators each includes a transducer on the surface of the piezoelectric layer such that the transducer is between the piezoelectric layer and the dielectric layer. The capacitor includes a first plate on the surface of the piezoelectric layer such that the first plate is between the piezoelectric layer and the dielectric layer and a second plate over the first plate such that the second plate and the first plate are separated by at least a portion of the dielectric layer.

Acoustic filtering circuitry including capacitor

Disclosed embodiments include a surface acoustic wave device having electrode period, electrode width, and/or ratio of electrode width to electrode period varied in a prescribed manner.

High coupling, low loss saw filter and associated method

The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM.

Routing under bond pad for the replacement of an interconnect layer

An acoustic wave device operable as a piston mode wave guide includes electrodes forming an interdigital transducer on a surface of the piezoelectric substrate, wherein each of the plurality of electrodes is defined as having a transversely extending center region and transversely opposing edge regions for guiding an acoustic wave longitudinally through the transducer. A Silicon Oxide overcoat covers the transducer and a Silicon Nitride layer covers the Silicon Oxide overcoat within only the center and edge regions. The thickness of the Silicon Nitride layer is sufficient for providing a frequency modification to the acoustic wave within the center region and is optimized with a positioning of a Titanium strip within each of the opposing edge regions. The Titanium strip reduces the acoustic wave velocity within the edge regions with the velocity in the edge regions being less than the wave velocity within the transducer center region.

Acoustic wave guide device and method for minimizing trimming effects and piston mode instabilities

The present invention, in one aspect, provides an integrated circuit that comprises a first region of transistors having gate structures with a low dopant concentration, and a second region of transistors having gate structures with a dopant concentration substantially higher than the gate structures of the first region, and wherein the transistors in the first region comprise a substantial portion of the integrated circuit. The transistors may include a resistor region located between an upper portion of the gate and the gate dielectric.

Semiconductor device and process for reducing damaging breakdown in gate dielectrics

A SAW device having metal electrodes on a surface of the piezoelectric substrate includes a dielectric layer deposited on the surface. Depositing the layer results in seams extending upward from the electrodes extending above the surface of the substrate. An additional seam results from one seam extending from one electrode joining a second seam extending from an adjacent electrode within the dielectric layer and is generally formed above the height of the electrodes. The additional seam is removed through planarization or the like. The dielectric layer may be further planarized for providing a thickness of the dielectric layer above the electrodes as desired.

Temperature compensated surface acoustic wave device and method having buried interdigital transducers for providing an improved insertion loss and quality factor

Improved coupling coefficients and desirable filter characteristics are exhibited in a SAW filter including an electrode pattern deposited on a piezoelectric substrate bonded directly to an anti-reflective layer, wherein the anti-reflective layer is bonded to a carrier through an adhesive layer such that a preselected thickness of the anti-reflective layer is sufficient for enhancing an acoustic match between the piezoelectric substrate and the adhesive layer.

Bonded wafer SAW filters and methods

A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.

Transistor fabrication method

The invention, in one aspect, provides a semiconductor device (), including transistors (), dielectric layers () located over the transistors (), interconnects () formed within the dielectric layers (), and a test structure () located adjacent a hot-spot () of the semiconductor device () and configured to monitor a real-time operational parameter of at least one of the transistors () or interconnects ().

Thermal monitoring and management of integrated circuits

An acoustic wave device includes electrodes carried on a surface of a piezoelectric material and an array of reflective obstacles such that elastic energy resulting from a piezoelectric effect is preferentially directed along a primary wave propagation path. The array of reflective obstacles are positioned generally parallel to the surface of the piezoelectric material and redirect acoustic waves typically reflected in other than a desirable direction to along a desired direction generally along the primary propagation path. The obstacles improve performance for SAW and BAW devices by effecting reflected energy and suppressing spurious modes.

Acoustic wave device employing reflective elements for confining elastic energy

A solder bump structure and an under bump metallurgical structure. An upper surface of a semiconductor substrate comprises a first conductive pad () disposed thereon. A passivation layer () overlies the upper surface. A second conductive pad () is disposed in an opening () in the passivation layer and in contact with the first conductive pad. The under bump metallurgical structure () encapsulates the second conductive pad, covering an upper surface and sidewalls surfaces of the second conductive pad, protecting both the first and the second conductive pads from environmental and processing effects. According to the present invention, the conventional second passivation layer is not required. Methods for forming the various structures are also presented.

Structure and method for fabricating flip chip devices

An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

Integrated circuit device incorporating metallurgical bond to enhance thermal conduction to a heat sink

Disclosed herein are novel damage detection circuitries implemented on the periphery of a semiconductor device. The circuitries disclosed herein enable the easy identification of cracks and deformation, and other types of damage that commonly occur during test and assembly processes of semiconductor devices.

Semiconductor with damage detection circuitry

Integrated circuit device incorporating metallurigical bond to enhance thermal conduction to a heat sink

Growing community of inventors

Orlando, FL, United States of America

Taeho Kook