Micron Technology Incorporated

Semiconductor Components Industries, LLC

Aptina Imaging Corporation

Taehee Cho

Chiajen Lee

Sandor L Barna

Kwang-Bo Cho

Andrew M Lever

Ashirwad Bahukhandi

Isao Takayanagi

Nikolai E Bock

Dongsoo Kim

Ju-Hyung Kim

Successive approximation register (SAR) and ramp analog to digital conversion (ADC) methods, systems, and apparatus are disclosed. An analog voltage signal may be converted into a multiple bit digital value by generating bits of the multiple bit digital value by performing a SAR conversion on the analog voltage signal, where the bits corresponding to a SAR voltage level, and generating other bits of the multiple bit digital value by performing one or more ramp conversions on the analog voltage signal, the ramp conversion comparing the analog voltage signal to a ramp of voltage levels based on the SAR voltage level. The SAR and ramp ADC can provide multi-sampling using one SAR conversion and multiple ramp conversions. The SAR can set the voltage level of a first ramp of a multiple ramp conversion, which can then be used to preset the voltage level prior to subsequent ramps.

Ramp and successive approximation register analog to digital conversion methods, systems and apparatus

An imager may include an imaging die that is stacked with an image processing die. The imaging die may generate output signals from received light. The image processing die may process the output signals. Through-silicon vias of the imaging die or solder balls may electrically couple the imaging die to the image processing die and convey the output signals to the image processing die. The imaging die may include a pixel array that generates pixel signals from the received light. The image processing die may generate control signals that control the imaging die and are conveyed to the imaging die over the through-silicon vias or solder balls.

Imagers with stacked integrated circuit dies

An electronic device may have one or more analog-to-digital converters (ADCs). The ADCs may be used in digitizing signals from an image sensor. In order to ensure that input signals received by an ADC are not clipped, the input signals may be positively or negatively offset by a desired amount. Offsetting the input signals may ensure that the offset input signals wall within the acceptable input range of the ADCs. Offset injection may be accomplished using capacitors that are also used for analog-to-digital conversion. As an example, the ADC may be a successive approximation-type ADC that uses capacitors in a binary search for the digital value most accurately representing an input analog value. The capacitors of the ADC may be used for the successive approximation process and for offset injection. The offset injection may be digitally canceled out following digitization of the input analog signal.

Offset injection in an analog-to-digital converter

Electronic devices may include image sensors having image sensor pixels. The pixels may be coupled to analog to digital converter (ADC) circuitry. The ADC may include a hybrid successive approximation register (SAR) ADC and ramp-compare ADC. The ramp-compare ADC may be controlled by count bits. The hybrid ADC may be subject to non-idealities at the transition between data conversion using the SAR ADC and the ramp-compare ADC. A voltage offset may be injected to the ramp-compare ADC to compensate for voltage glitches. The ramp-compare ADC may have an output range that is insufficiently matched to a least significant bit of the SAR ADC. An error correction bit may be added to the count bits to increase the output range of the ramp-compare ADC to match the SAR least significant bit. The ramp-compare ADC may include gain control circuitry to further match the output range to the SAR least significant bit.

Methods and apparatus for performing code correction for hybrid analog-to-digital converters in imaging devices

A programmable gain amplifier (PGA) includes a sample-and-hold (S&H) stage which provides an input capacitance value for storing a charge. The PGA also includes an amplifying stage, which has a gain dependent on the input capacitance value. The amplifying stage is configured to provide a variable gain, while the S&H stage is configured to provide a substantially constant input capacitance value, regardless of the gain.

Variable gain stage having same input capacitance regardless of the stage gain

An amplifier, which may be used in a pipelined analog-to-digital converter, includes a first amplifier stage driving a second amplifier stage. At least one compensation capacitor is coupled to provide negative feedback through the capacitor from the second amplifier stage to the first amplifier stage. The slew rate of the amplifier is enhanced by substantially reducing the negative feedback coupled through the capacitor during a period following the transition of a signal applied to an input terminal of the amplifier. If the first stage of the amplifier has complementary signal nodes, the negative feedback coupled through the capacitor may be reduced, for example, by closing a switch coupled between first and second complementary nodes of the first amplifier stage.

High slew rate amplifier, analog-to-digital converter using same, CMOS imager using the analog-to-digital converter and related methods

A method and apparatus for reducing temporal row noise by sampling pixel signals and a separate signal representing noise. The pixel signals and noise signals are used in a correlated differential sampling operation.

Method and apparatus for reducing temporal row-wise noise in imagers

A method and apparatus for reducing settling time of a switched capacitor amplifier. The method includes disconnecting first and second capacitors from an amplifier. When the first and second capacitors are disconnected from the amplifier, they are charged by respective first and second input signals. The apparatus includes a plurality of sampling capacitors, each configured to sample a respective one of a plurality of signals during a sampling phase, an amplifier, and a plurality of decoupling switches configured to isolate the sampling capacitors from the amplifier during the sampling phase and to connect the plurality of sampling capacitors to the amplifier during the amplifying phase.

Method of and apparatus for reducing settling time of a switched capacitor amplifier

A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry, before the amplifier configuration of the stages/channels is switched. The discharging act occurs when a short reset pulse is generated between two clock phases. The short reset pulse is applied to a switch connected to the operational amplifier input. When the reset pulse closes the switch, a discharge path is created and any parasitic capacitance at the operational amplifier input is discharged through the path. The discharging of the parasitic capacitance substantially mitigates the memory effect and the problems associated with the memory effect.

Sharing operational amplifier between two stages of pipelined ADC and/or two channels of signal processing circuitry

In accordance with one embodiment, there is provided a pipelined analog-to-digital converter (ADC) device. The pipelined ADC includes a first stage and a second stage. The first and second stages are configured to share a sub-ADC and a sub-digital-to-analog converter.

Method and apparatus for decreasing layout area in a pipelined analog-to-digital converter

A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry. The operational amplifier contains two input circuits that are time multiplexed in a manner that allows capacitance to be discharged at one input circuit while the other input circuit is inputting signals into the amplifier. The discharging of the parasitic capacitance substantially mitigates the memory effect and the problems associated with the memory effect.

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Irvine, CA, United States of America

Taehee Cho