Samsung Display Co., Ltd.

Samsung Displayco., Ltd.

Samsung Display Go., Ltd.

Taegon Im

Sooyeon Kim

Wontae Kim

Boyeon Kim

Jae-Han Lee

Junghwan Cho

Dae-Sik Lee

Min-Soo Choi

Youngsup Kwon

Eun Chul Shin

JiYe Lee

Jong Jae Lee

Sun-Koo Kang

Gwangsoo Ahn

Hee-Jeong Seo

Hwanwoong Lee

Guhui Jo

Min-Gyu Kim

Mingyu Kim

Jihyun Kim

Yanguk Nam

Kyunho Kim

Myoung-Soo Kim

Jung Hwan Cho

Moonshik Kang

Songyi Han

Dongwon Park

Byungkil Jeon

Byung-kyou Min

Jinyoung Jeon

Young-Sup Kwon

Wonhyoung Kang

Jintaek Hong

Eunchul Shin

Youngmin Bae

A display device includes a display panel including a plurality of pixel rows, a driving controller that generates a clock signal and a gate driver that provides scan signals and sensing signals to the plurality of pixel rows in response to the clock signal, wherein the clock signal includes a plurality of first pulses in an active period of a frame period and a plurality of second pulses in a vertical blank period of the frame period, and a width of at least one of the plurality of second pulses is different from a width of each of the plurality of first pulses.

Display device and method of driving the same

A display device includes a display panel including a plurality of pixels and a plurality of data lines connected to the pixels, and a data driver which provide a plurality of data voltages to the data lines. The data driver includes a plurality of channels, where each of the channels outputs an ndata voltage in an nhorizontal period, and outputs an (n+1)data voltage in an (n+1)horizontal period, where n is a natural number, a common line, a plurality of data switches, which selectively connect the channels to the data lines, respectively, a plurality of common switches, each of which selectively connects a corresponding one of the channels to the common line, and a voltage sensor which senses a common voltage of the common line.

Data driver, display device including the same, and method for driving display device

Provided is a data driver including a digital to analog converter configured to convert image signal data into a plurality of data voltages, and an output buffer unit including a plurality of channels for outputting the plurality of data voltages. The output buffer unit includes a plurality of output blocks. Each output block includes one or more channels. Data voltages outputted from a first output block among the plurality of output blocks are delayed with a first time difference. Data voltages outputted from a second output block among the plurality of output blocks are delayed with a second time difference which is different from the first time difference.

Data driver and display device having same

A display device may include a display panel including a gate line, a data line, and a pixel electrically connected to the gate line and the data line, where display panel displays an image based on input image data, a gate driver which outputs a gate signal to the gate line, a data driver which outputs a data voltage to the data line, and a power supply voltage generator which provides a driving voltage to the display panel, the gate driver and the data driver. The power supply voltage generator generates a gate clock signal based on an on-clock signal and an off-clock signal and changes a count value of the on-clock signal or the off-clock signal when the gate clock signal is an abnormal signal.

A display apparatus includes a display panel, a gamma reference voltage generator and a data driver. The gamma reference voltage generator is configured to generate a gamma reference voltage. The gamma reference voltage includes a gamma amplifier configured to output the gamma reference voltage. The data driver is configured to generate a data voltage based on the gamma reference voltage and to output the data voltage to the display panel. A polarity of an offset voltage of the gamma amplifier is inverted alternately in a unit of one frame and in a unit of two frames.

Display apparatus and method of driving the same

A display device may include a data driver that outputs a previous data voltage and a current data voltage, respectively, at an output terminal, to be applied to a pixel of a display panel in respective time intervals. A switch is controlled to open and close a circuit path between the output terminal and a data line coupled to the pixel. A capacitor stores an overdriving voltage. At least one further switch selectively applies the overdriving voltage to the data line from the capacitor when the circuit path is open and thereby enables a rapid transition of a voltage level of the data line between the previous and current data voltages, when the current and previous data voltages are to differ by more than a predetermined amount. As an example, the rapid transition between the previous and current data voltages may serve to minimize a color mixture phenomenon between pixels connected to a common data line and representing different colors.

Display device

A display device includes a display panel including first and second panel pads electrically connected to each other, a connection board including first and second connection board pads connected to the first and second panel pads, respectively, an output pad, and a driving circuit. The driving circuit includes a pull-up resistor connected between a first voltage terminal and a first node, and a comparator configured to compare a voltage at the first node with a reference voltage and to output a contact test signal corresponding to a comparison result to the output pad. The first connection board pad is electrically connected to the first node, and the second connection board pad is connected to a second voltage terminal.

Display device including a connection board and a method for testing pad connection thereof

A display device includes a display panel including a plurality of data lines, and a plurality of pixels coupled to the plurality of data lines, a data driver including a plurality of channels providing data voltages to the plurality of pixels through the plurality of data lines, and a controller configured to control the data driver. The plurality of channels is grouped into first through N-th channel groups, where N is an integer greater than 1. The first through N-th channel groups sequentially initiate first dummy data voltage output operations in a first order from the first channel group to the N-th channel group in a first blank period before an active period, and sequentially finish second dummy data voltage output operations in a second order from the N-th channel group to the first channel group in a second blank period after the active period.

Display device, and method of operating the display device

A display apparatus includes a display panel, a data driver, a power voltage generator, a driving controller and a timing compensator. The display panel displays an image based on input image data. The data driver outputs a data voltage to the display panel. The power voltage generator outputs a data power voltage to the data driver. The driving controller controls a driving timing of the data driver. The timing compensator changes an output timing of the data voltage of the data driver when a feedback data power voltage is less than a reference data power voltage at a start point of an active period.

Power voltage generating circuit compensating ripple of a data power voltage and display apparatus including the same

A display device includes a signal controller configured to provide data and a frame control signal, a display panel including first to m-th data line groups, and a data driver configured to receive the data and the frame control signal, and output a data signal corresponding to the data to the first to m-th data line groups. The data driver includes first to m-th data driving circuit units electrically connected to the first to m-th data line groups in one-to-one correspondence, Each of the first to m-th data driving circuit units includes a clock adjustment unit configured to generate a second clock signal using a first clock signal and the frame control signal. The second clock signal controls an output timing of the data signal to be transmitted to a first channel among a plurality of channels of each of the first to m-th data line groups.

Display device controlling an output timing of a data signal

A display device according to an embodiment of the inventive concept includes a data driving unit, a gate driving unit, a signal control unit for controlling driving of the data driving unit and the gate driving unit, and a display panel. The data driving unit generates an internal clock signal for outputting data voltages corresponding to image data, and the display panel displays an image corresponding to the data voltages in response to a gate driving signal outputted from the gate driving unit. The data driving unit includes a filtering unit for converting a first frequency control signal received from the signal control unit so as to generate a second frequency control signal, and a clock training unit for training a clock signal received from the signal control unit so as to generate the internal clock signal in response to the second frequency control signal.

A gate driving circuit includes a shift register configured to generate a plurality of output signals based on at least one clock signal, a plurality of output buffers configured to generate a plurality of gate signals by amplifying the output signals and to sequentially output the gate signals to a plurality of gate lines in a display panel, a detector configured to sequentially sense the gate signals and to compare each of the gate signals to a reference voltage, and a dummy output buffer configured to be coupled between the shift register and a gate line of the gate lines instead of an output buffer of the output buffers when a voltage level of a corresponding gate signal from the output buffers is less than a voltage level of the reference voltage.

Gate driving circuit and display device having the same

A display device including: a display panel including a plurality of pixels; and a data driver configured to arrange the display panel into a plurality of pixel blocks, and to output a data voltage with different slew rates to the plurality of pixel blocks, wherein the slew rates are based on distances of the plurality of pixel blocks from the data driver, wherein a boundary between adjacent pixel blocks with different slew rates is changeable.

Display device having a variable pixel block boundary

A display device having a charging compensation circuit to reduce/eliminate display stains based on pixels being charged at unequal charging rates. A data driving circuit of a display device includes an output circuit for converting an image signal into a data signal in response to a clock signal, and providing the data signal to a plurality of data lines, and a clock generating and compensating circuit for receiving a main clock signal and generating the clock signal, wherein the clock generating and compensating circuit detects a slew rate of the data signal provided to at least one of the plurality of data lines, and adjusts a phase of the clock signal depending on the detected slew rate.

Growing community of inventors

Gwangmyeong-si, South Korea

Taegon Im