Fairchild Semiconductor Corporation

Taeghyun Kang

Kenneth Patrick Snowdon

Alister Young

Yongliang Li

Christopher A Bennett

Duane Connerney

This document discusses, among other things, an auxiliary self-protecting transistor circuit, system, and method configured to protect a complementary metal-oxide semiconductor (CMOS) transistor. The auxiliary self-protecting transistor circuit can include an ESD device including a gate terminal, a drain terminal, and a source terminal. The ESD device is configured to be coupled to an isolation region of a complementary metal-oxide semiconductor (CMOS) transistor, and can provide a discharge path between the isolation region of the CMOS transistor and the source terminal of the ESD device. The isolation region of the CMOS transistor can include a blocking junction, such as an n-doped isolation well (niso), a p-type well (pwell), or one or more other blocking junctions.

Auxiliary self-protecting transistor structure

This document discusses, among other things, a biased electrostatic discharge (ESD) circuit and method configured to reduce capacitance of an ESD structure with little to no change in other ESD structure parameters. A bulk terminal of an ESD device can be negative biased to reduce a drain terminal to source terminal capacitance of the ESD device. A charge pump can be configured to provide a negative bias to the bulk terminal of the ESD device. In certain examples, the gate terminal of the ESD device can be coupled to the source terminal of the ESD device, such as through a resistor, and the source terminal can be coupled to ground.

Biased ESD circuit

A system includes undervoltage protection circuitry coupled in parallel with electronic circuitry configured to receive a supply voltage from a power supply. The undervoltage protection circuitry is configured to shunt undervoltage current resulting from an undervoltage transient in the supply voltage away from the electronic circuitry.

Undervoltage protection system

This document discusses among other things apparatus and methods for reducing ESD damage to buffer circuits. In an example, an output buffer can include an output, a first transistor configured to couple the output to a high logic supply rail, a second transistor configured to couple the output node to a low logic supply rail, pre-driver logic configured to drive a gate of the first transistor and a gate of the second transistor, and a first resistor configured to reduce electrostatic discharge (ESD) induced current between the first transistor and the pre-driver logic.

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Scarborough, ME, United States of America

Taeghyun Kang