Hynix Semiconductor Inc.

Hyundai Electronics Industries Co. Ltd.

Tae-Yun Kim

Kyoung-Nam Kim

Jun-Gi Choi

Hwang Hur

Sang-Jin Byeon

A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.

Pulse control device

Provided are a delay locked loop (DLL) and a method for generating a divided clock therein. In the DLL, a width of a reference frequency for phase comparison can be changed depending on a magnitude of an operating frequency. In the DLL, a clock buffer receives a clock equal to an external clock and generates an internal clock. An enable clock generator generates a 1-period enable clock or a 2-period enable clock using a command signal generated for performing a predefined operation. The command signal is generated according to an address command signal inputted from an exterior. A clock divider divides the internal clock to generate a divided clock. The divided clock is controlled by the 1-period enable clock or the 2-period enable clock, such that the divided clock is made to be a 1-period based dividing clock or a 2-period based dividing clock.

Delay locked loop in semiconductor memory device and method for generating divided clock therein

Provided is a pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.

An internal voltage generator for use in a semiconductor memory device includes a first voltage detection unit, a second voltage detection unit, a detection signal generation unit, and an internal voltage generation unit. The first voltage detection unit detects a voltage level of an internal voltage changing linearly depending on a temperature variation to output a first detection signal. The second voltage detection unit detects the voltage level having a constant value without concerning the temperature variation to output a second detection signal. The detection signal output unit combines the first and the second detection signal to generate a combined detection signal for detecting the voltage level linearly varying according to the temperature variation in a first range of temperature and detecting the voltage level having the constant value in a second range of temperature.

Internal voltage detection circuit

A delay detecting apparatus detects delay amounts of delay elements in a semiconductor device by using a test mode. The semiconductor device comprises a delay signal detecting unit for detecting delays of delay elements in the semiconductor device by using a signal that is synchronized with an external clock, and a delay signal outputting unit for outputting a delayed signal from the delay signal detecting unit to a data pad by using the signal that is synchronized with the external clock.

Delay detecting apparatus of delay element in semiconductor device and method thereof

A memory device for adjusting a write recovery time includes a synchronous write recovery time controlling block which receives a control signal for performing an auto-precharge operation and delays out the control signal as long as a certain clock section of the operational clock corresponding to the write recovery time, an asynchronous write recovery time controlling block for delaying out the control signal coupled thereto as long as a fixed delay time corresponding to the write recovery time, a selecting block for choosing the synchronous write recovery time controlling block or the asynchronous write recovery time controlling block, and an auto-precharge controlling block which outputs as an auto-precharge execution signal used in performing the auto-precharge operation a signal outputted from the synchronous write recovery time controlling block or the asynchronous write recovery time controlling block in response to a write command.

Synchronous memory device capable of controlling write recovery time

A partial array self refresh (PASR) control apparatus for use in a semiconductor memory device having a plurality of banks includes: a bank deselection unit having a plurality of bank deselection signal output units for receiving a plurality of PASR code signals, wherein input terminal lines of each bank deselection signal output unit and signal lines of the plurality of PASR code signals are crossed each other and are selectively coupled each other.

Bank based self refresh control apparatus in semiconductor memory device and its method

A redundancy circuitry is used in a memory device for repairing defects in a packaged memory having registers by using antifuse. The redundancy circuitry includes: an anticell for storing data to be replaced; a temporary anticell for storing the data temporarily; a row and a column antifuse composed of antifuse and anti enable fuse corresponding to a row and column address, respectively; an antifuse controller for controlling the programming of the antifuse; a voltage supplier for supplying a voltage to program the antifuse; a row and a column comparators for comparing the programmed row and column antifuses and the external input address, respectively; an anti-controller for controlling to provide data from the anticell on a read operation and to temporarily store the external data to the temporary anticell on a write operation based on the comparison signals; a restore controller for, based on the row address on a restore operation, transferring the external data identical to the programmed fuse address to the anticell; and a channel selection memory for storing the channel address for pre-fetch and restore operations provided during read and write operations.

Redundancy circuitry for repairing defects in packaged memory having registers

An apparatus for pre fetching and restoring data stored in memory cells in a semiconductor memory device includes a bit line sense amplifying unit and a control unit. The bit line sense amplifying unit senses the data stored in the memory cells in response to a bit line sense amplifier driving signal. The control unit drives the bit line sense amplifying unit before data applied on pairs of bit lines are transferred to pairs of data bus lines in response to a control signal during a pre fetching operation. Additionally, the control unit drives the bit line sense amplifying unit after data applied on the pairs of bit lines via the pairs of data bus lines is transferred to the pairs of bit lines in response to the control signal.

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Kyoungki-do, South Korea

Tae-Yun Kim