Samsung Electronics Co., Ltd.

Tae-Young Yoon

Hyo-Soon Kang

Sun-Won Kang

Joon-Young Park

Dae-ho Lee

Hee-jin Lee

Seok-hong Kwon

Doo-Hee Hwang

A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof. The stack semiconductor package includes a second semiconductor package disposed on the first semiconductor package, and includes a second package substrate. A first sub-chip and a second sub-chip is mounted on the second semiconductor package and arranged side by side extending along a direction of a first side portion of the second package substrate. Each of the first and second sub-chips includes second chip pads arranged along a side portion thereof. Connection wiring paths between interface portions and connection pads may be reduced and simplified, thereby preventing connection wires from being tangled. Moreover, connection wiring paths between a logic chip and a memory chip may be minimized, thereby providing high speed performance.

Stack semiconductor package

A printed circuit board (PCB) includes a base substrate including upper and lower surfaces, a plurality of solder ball pads separately formed on the lower surface of the base substrate in a radial direction and forming one or more radial pad groups, a plurality of first traces respectively connected to the plurality of solder ball pads and extending to an inside of the radial pad group, and a plurality of second traces respectively connected to the plurality of first traces and extending to an outside of the radial pad group.

Printed circuit board having traces and ball grid array package including the same

A package substrate may include an insulating substrate, a first land array, a second land array, a first plating line and a second plating line. The first land array may be arranged on a first surface of the insulating substrate. The second land array may be arranged on a second surface of the insulating substrate opposite to the first surface. The second land array may be electrically connected to the first land array. The second land array may include outer lands and inner lands. The first plating line may be connected to the outer lands. The second plating line may be connected between the outer lands and the inner lands. The second plating line may have a width narrower than that of the first plating line. The second plating line may be removed by applying a removing current to the first plating line prior to the first plating line.

Package substrate, method of manufacturing the package substrate and semiconductor package including the package substrate

A memory device is provided. The memory device includes a first semiconductor chip including a memory element and a peripheral circuit configured to write or read data in or from the memory element; and a second semiconductor chip configured to perform an input/output function of data or signals exchanged between an external device and the first semiconductor chip.

Growing community of inventors

Hwaseong-si, South Korea

Tae-Young Yoon