Samsung Electronics Co., Ltd.

Lg Display Co., Ltd.

Tsinghua University

Tae-Young Oh

Seung-Jun Shin

Hye-Ran Kim

Kyung-Soo Ha

Kwang-il Park

Seung-Jun Bae

Seong-Hwan Jeon

Si-hong Kim

Young-hun Kim

Seok-Jin Cho

Young-Soo Sohn

Young-Hwa Kim

Heung-Lyul Cho

Su-Yeon Doo

Jung-Hwan Park

Ji-Eun Jung

Kwnag-Il Park

Il-Pyo Hong

Jin-Hun Jang

Jong-Ho Lee

Seong-Jin Jang

Hwan Mook Kim

Hyun-Joong Kim

Hoi-ju Chung

Chul-Sung Park

Joo-sun Choi

Woogeun Rhee

Cheol Su Kim

Jang-Woo Ryu

Doo-Hwan Lee

Hyong-Ryol Hwang

Zhihua Wang

Gong-Heum Han

Jin-Hoon Jang

Si-Hong Kim

Tae-Seong Jang

Chan-yong Lee

Xueyi Yu

Seong-Won Son

Geun-tae Park

Tae-Sin Song

Yun-Seok Yang

He Rui

Hyung-Joon Chi

Young-Sang Hong

A memory system, including a memory controller and a memory, wherein the memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller mixes a second command with the first command and transmits the mixture of the first command and the second command. The memory changes command latch timing depends on the first or second mode.

Memory device and memory system

There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

Memory device for supporting command bus training mode and method of operating the same

A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

Clock synchronizing method of a multiple clock domain memory device

A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

Dynamic random access memory (DRAM) device and memory controller therefor

A memory device includes: a first memory bank and a second memory bank; a control logic configured to receive a command and control an internal operation of the memory device; and an error correction code (ECC) circuit configured to retain in a latch circuit first read data read from the first memory bank in response to a first masked write (MWR) command for the first memory bank based on a latch control signal from the control logic, generate a first parity from data in which the first read data retained in the latch circuit is merged with first write data corresponding to the first MWR command in response to a first write control signal received from the control logic, and control an ECC operation to retain in the latch circuit second read data read from the second memory bank based on the latch control signal.

Memory device having error correction function and operating method thereof

Memory device and method for supporting command bus training mode based on one data signal

Dynamic random access memory (DRAM) device, memory controller therefor, and memory system

Synchronous dynamic random access memory (SDRAM) device, memory controller therefor, and method of operating same

There are provided, a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

A semiconductor memory device includes a memory cell array and an address decoder. The memory cell array includes a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of dynamic memory cells coupled to word-lines and bit-lines, each of the plurality of memory blocks are divided into a plurality of row blocks by row block identity bits of a row address, and each of the of row blocks includes a plurality of sub-array blocks arranged in a first direction. The address decoder changes a physical row address of a memory cell that stores or outputs data based on a column address received with a write command or a read command.

Semiconductor memory devices and methods of operating semiconductor memory devices

Growing community of inventors

Seoul, South Korea

Tae-Young Oh