Samsung Electronics Co., Ltd.

Hyundai Motor Company

Postech Academy-industry Foundation

Tae-Young Chung

Chang-Hyun Cho

Cheol-Ju Yun

Jae-Goo Lee

Soo-Ho Shin

Yong-sung Kim

Yong-Sung Kim

Yoo-Sang Hwang

Jin-Woo Lee

Chang-hyun Cho

Ju-yong Lee

Ji-Young Kim

Ki-Nam Kim

Dong-jun Lee

Dae-je Chin

Mi-Kyung Park

Dong-Hwa Kwak

Ju-Yong Lee

Yoon-soo Chun

Eun-Cheol Lee

Hyung-Soo Uh

Joon-ho Sung

Yong-Seok Ahn

Sang-Bum Kim

Gwan-Hyeob Koh

Yong-Hoon Lee

Je-Min Park

Dong-Jun Lee

Joon Soo Han

Young-Pil Kim

Won-Suk Yang

Sung-Ho Jang

Sung-Hee Han

Keum-Jin Park

Jaesup Lee

Bum-Man Kim

Chun-Hyuk Lee

Yoo-sang Hwang

Bo-Young Song

Jae-Yun Shim

Dong-Su Ha

Yang-keun Park

Kyung-Taek Lee

Kyu-hyun Lee

Dae-Chul Jeong

Yong-Gyu Choi

Jang-Hyo Lee

Young-Kwan Ko

Byung-Hoon Yang

Kyu-Hynn Lee

A motor speed control method and system for improving the performance of a running resistance evaluation of a hybrid electric vehicle are provided. The method includes determining whether a vehicle satisfies a running resistance evaluation start condition. When the vehicle satisfies the running resistance evaluation start condition, the speed of a motor is adjusted, which adjusts an input speed of a transmission to be equal to an output speed of the transmission. A speed adjustment of the motor is then completed using the speed of the motor and the output speed of the transmission.

Motor speed control method and system for improving performance of running resistance evaluation

A leakage current-based delay circuit is provided, wherein the delay circuit may include a first transistor circuit and a second transistor circuit, each transistor circuit may include a p-type transistor, an n-type transistor, an n-node between a drain node of the p-type transistor and a gate node of the n-type transistor, and a p-node between a gate node of the p-type transistor and a drain node of the n-type transistor. The p-node of the second transistor circuit may be charged based on a power source voltage through the first transistor circuit during a first time interval of an input signal, and the n-node of the second transistor circuit may be discharged based on a ground voltage through the first transistor circuit during the first time interval.

Leakage current-based delay circuit

A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

Semiconductor device having vertical channels and method of manufacturing the same

A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region.

Metal oxide semiconductor (MOS) transistors having a recessed gate electrode

A recessed gate structure in a semiconductor device includes a gate electrode partially buried in a substrate, a blocking member formed in the buried portion of the gate electrode, and a gate insulation layer formed between the gate electrode and the substrate. The blocking member may effectively prevent a void or a seam in the buried portion of the gate electrode from contacting the gate insulation layer adjacent to a channel region in subsequent manufacturing processes. Thus, the semiconductor device may have a regular threshold voltage and a leakage current passing through the void or the seam may efficiently decrease.

Methods of forming recessed gate structures including blocking members, and methods of forming semiconductor devices having the recessed gate structures

Methods of manufacturing semiconductor devices are provided in which a first contact plug is formed on a first active region in a substrate and a second contact plug is formed on a second active region in the substrate. A height of an upper surface of the second contact plug from the substrate is greater than a height of an upper surface of the first contact plug from the substrate. A third contact plug is formed on the second contact plug. A first spacer is formed on a side surface of the third contact plug. A third interlayer insulation layer is formed that covers the third contact plug. The third interlayer insulation layer is patterned to form a third opening that exposes the first contact plug. A fourth contact plug is formed in the third opening that is electrically connected to the first contact plug.

Methods of manufacturing semiconductor devices having contact plugs in insulation layers

According to some embodiments of the invention, transistors have channel regions between channel-portion holes. Methods of forming the same include at least two channel-portion holes disposed in a semiconductor substrate. Line patterns are formed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate to fill the channel-portion holes. A channel region is disposed in the semiconductor substrate below the line patterns. At this time, the channel region is formed between the channel-portion holes and also covers lower portions of the channel-portion holes. Driving current capability and refresh characteristics of DRAMs utilizing the inventive transistors are improved.

Transistors having a channel region between channel-portion holes and methods of forming the same

A semiconductor integrated circuit device having a 6Flayout is provided. The semiconductor integrated circuit device includes a substrate; a plurality of unit active regions disposed in the substrate and extending in a first direction; first and second access transistors including first and second gate lines disposed on the substrate and extending across the unit active regions in a second direction forming an acute angle with the first direction; a first junction area disposed in the substrate between the first and second gate lines and second junction areas disposed on sides of the first and second gate lines where the first junction area is not disposed; a plurality of bitlines disposed on the substrate and extending in a third direction forming an acute angle with the first direction; and a plurality of bitline contacts directly connecting the first junction area and the bitlines.

Semiconductor integrated circuit device and method of fabricating the semiconductor integrated circuit device

Disclosed are methods for forming FinFETs using a first hard mask pattern to define active regions and a second hard mask to protect portions of the insulating regions between active regions. The resulting field insulating structure has three distinct regions distinguished by the vertical offset from a reference plane defined by the surface of the active regions. These three regions will include a lower surface found in the recessed openings resulting from the damascene etch, an intermediate surface and an upper surface on the remaining portions of the lateral field insulating regions. The general correspondence between the reference plane and the intermediate surface will tend to suppress or eliminate residual gate electrode materials from this region during formation of the gate electrodes, thereby improving the electrical isolation between adjacent active regions and improving the performance of the resulting semiconductor devices.

Fabrication of local damascene finFETs using contact type nitride damascene mask

A transistor includes substrate having an active region therein. The active region includes a recess therein having opposing sidewalls and a surface therebetween. A protrusion extends from the surface of the recess between the opposing sidewalls thereof. The transistor further includes a gate insulation layer on the protrusion in the recess, a gate electrode on the gate insulation layer in the recess, and source/drain regions in the active region on opposite sides of the gate electrode and adjacent to the opposing sidewalls of the recess. The gate electrode includes portions that extend into the recess between the protrusion and the opposing sidewalls of the recess. Related methods of fabrication are also discussed.

Methods of fabricating field effect transistors including recessed forked gate structures

A self-aligned inner gate recess channel in a semiconductor substrate includes a recess trench formed in an active region of the substrate, a gate dielectric layer formed on a bottom portion of the recess trench, recess inner sidewall spacers formed on sidewalls of the recess trench, a gate formed in the recess trench so that an upper portion of the gate protrudes above an upper surface of the substrate, wherein a thickness of the recess inner sidewall spacers causes a center portion of the gate to have a smaller width than the protruding upper portion and a lower portion of the gate, a gate mask formed on the gate layer, gate sidewall spacers formed on the protruding upper portion of gate and the gate mask, and a source/drain region formed in the active region of the substrate adjacent the gate sidewall spacers.

Method of forming self-aligned inner gate recess channel transistor

Semiconductor devices including an isolation layer on a semiconductor substrate are provided. The isolation layer defines an active region of the semiconductor substrate. The device further includes an upper gate electrode crossing over the active region and extending to the isolation layer and lower active gate electrode. The lower active gate electrode includes a first active gate electrode extending from the upper gate electrode to the active region and a second active gate electrode below the first active gate electrode and having a greater width than a width of the first active gate electrode. The device further includes a lower field gate electrode that extends from the upper gate electrode to the isolation layer and has a bottom surface that is at a lower level than a bottom surface of the active gate electrode such that the sidewalls of the active region are covered below the lower active gate electrode. Related methods of fabricating semiconductor devices are also provided herein.

Methods of fabricating semiconductor devices including transistors having recessed channels

Metal oxide semiconductor (MOS) transistor having a recessed gate electrode and methods of fabricating the same

Growing community of inventors

Gyeonggi-do, South Korea

Tae-Young Chung