Samsung Electronics Co., Ltd.

International Business Machines Corporation

Tae Yong Kwon

Oh Seong Kwon

Jung Han Lee

Yong Hee Park

Kyung Yub Jeon

Soo Yeon Jeong

Byoung-Gi Kim

Jong Ryeol Yoo

Ki Hwan Lee

Jung Hwan Kim

Jae Hwan Lee

Kang Ill Seo

Sang Su Kim

Chang Jae Yang

Yeon Cheol Heo

Ki Sik Choi

Hwan Wook Choi

Sang Hyuk Hong

A semiconductor device includes a substrate having first and second regions, first fin groups spaced along a first direction on the first region, each of the first fin groups including adjacent first and second fins having longitudinal directions in a second direction intersecting the first direction, and third to fifth fins spaced along a third direction on the second region, the third to fifth fins having longitudinal directions in a fourth direction intersecting the third direction. The third through fifth fins are at a first pitch, the first and second fins are at a second pitch equal to or smaller than the first pitch, each of the first fin groups is at a first group pitch greater than three times the first pitch and smaller than four times the first pitch, and a width of the first and second fins is same as width of the third fin.

Method for fabricating semiconductor device

Semiconductor device and method for fabricating the same

A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

Vertical tunneling field effect transistor and method for manufacturing the same

Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a channel region that protrudes from an upper surface of a substrate in a vertical direction, forming a gate insulator layer on a side of the channel region, after forming the gate insulator layer, forming a top source/drain on the channel region, and forming a gate electrode on the gate insulator layer.

Vertical field-effect transistor (VFET) devices and methods of forming the same

A method of fabricating a gate all around semiconductor device is provided. The method includes: providing a semiconductor substrate having a plurality of active fins extending in a first direction in a first region and a second region next to the first region, a plurality of gate all around channels stacked above each of the plurality of active fins, and a plurality of gate openings extending in a second direction across the first and second regions and crossing the plurality of active fins, in which the plurality of gate openings include cave-like gate spaces between each of the plurality of active fins and one adjacent gate all around channel and between two adjacent gate all around channels, forming a dielectric layer in the first and second regions on bottom and sidewalls of each of the plurality of gate openings, and on and surrounding each of the plurality of gate all around channels and filling a first portion of each of the cave-like gate spaces, forming first work function metal in the first and second regions on the dielectric layer with the first work function metal filling a second portion of each of the cave-like gate spaces, forming first carbon-based mask in the first and second regions by a chemical vapor deposition (CVD) process to fill the plurality of gate openings to a height at least covering all the plurality of gate all around channels, forming second carbon-based mask in the first and second regions on top of the first carbon-based mask to a height above the plurality of gate openings, removing the first and second carbon-based masks in the second region, removing the first work function metal in the second region through etching using remaining first and second carbon-based masks in the first region as an etching mask, removing the remaining first and second carbon-based masks in the first region, and forming second work function metal on the dielectric layer in the second region, and on the first work function metal in the first region.

Method of fabricating gate all around semiconductor device

Semiconductor devices are provided. The semiconductor devices include active fins including a buffer layer disposed on a substrate and a channel layer disposed on the buffer layer and having a first second lattice constant higher than a lattice constant of the buffer layer, a gate structure covering the channel layer and intersecting the active fins, sidewall spacers disposed on both sidewalls of the gate structure, and capping layers disposed to contact lower surfaces of the sidewall spacers and having a width substantially the same as a width of the lower surfaces of the sidewall spacers.

Semiconductor device having strained channel layer and method of manufacturing the same

An apparatus to manufacture a semiconductor includes a plasma-limiting device to limit a plasma region in a reaction chamber. The plasma-limiting device includes a first limiting device to limit the plasma region in the reaction chamber to a first plasma region, a second limiting device to limit the plasma region in the reaction chamber to a second plasma region having an area larger than an area of the first plasma region, and a driving device to simultaneously move the first and second limiting devices to vary the plasma region.

Apparatus to manufacture semiconductor

Growing community of inventors

Suwon-si, South Korea

Tae Yong Kwon