Samsung Electronics Co., Ltd.

Tae-Yeol Kim

Dohyun Lee

Heonbok Lee

Daeyong Kim

Jun-soo Kim

Hyon-wook Ra

Seo-bum Lee

Chung-hwan Shin

Donghee Seo

Jae-Jik Baek

Hyun-Seung Song

Ji Won Kang

Rak Hwan Kim

Chung Hwan Shin

Jeong Ik Kim

Jun Ki Park

Geun Hee Jeong

Jinwoo Choi

A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.

Semiconductor devices including resistor structures

A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

Semiconductor devices and methods of fabricating the same

A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.

Semiconductor device

A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.

Method for forming a semiconductor device

Provided are semiconductor devices and methods for fabricating the same. A method for fabricating a semiconductor device includes: forming an interlayer dielectric layer including an opening in which a lower conductive layer is exposed; forming a barrier layer on the interlayer dielectric layer and on the lower conductive layer the opening; forming an anti-seed generation region on a surface of the barrier layer which is provided on a top surface of the interlayer dielectric layer and an upper sidewall of the opening; and filling the opening with conductive material to form a conductive layer.

Methods for fabricating semiconductor devices including a seed generation accelerating layer

Growing community of inventors

Hwaseong-si, South Korea

Tae-Yeol Kim