Samsung Electronics Co., Ltd.

Tae-Wook Oh

Woong Seo

Soo-Jung Ryu

Young-chul Cho

Il-hyun Park

Yoon-Jin Kim

Bernhard Egger

Won-sub Kim

Il-Hyun Park

A method of controlling access to a multi-bank memory, and an apparatus to perform the method, is provided. For the access control, a stride register is provided to store stride values determined by a processor during a run time. A memory controller controls access to a logical block in row and column directions, in an interleaved manner, the logical block having a width determined according to the stride values stored in the stride register. Accordingly, simultaneous access to a plurality of pieces of data at successive addresses adjacent in the row and column directions may be made.

Apparatus to access multi-bank memory

An apparatus and method for scheduling an instruction are provided. The apparatus includes an analyzer configured to analyze dependency of a plurality of recurrence loops and a scheduler configured to schedule the recurrence loops based the analyzed dependencies. When scheduling a plurality of recurrence loops, the apparatus first schedules a dominant loop whose loop head has no dependency on another loop among the recurrence loops.

Apparatus and method for scheduling instruction

Provided are a simulator of a multi-core system employing reconfigurable processor (RP) cores and a method of simulating a multi-core system employing RP cores. The simulator includes a structure builder to receive a structure definition file defining a structure of a system, select components described in the structure definition file from a component library, and fill a data structure with the selected components to generate a structure model of a multi-core system, and a simulation engine to execute an application program according to the structure model and output the result.

Simulator of multi-core system employing reconfigurable processor cores and method of simulating multi-core system employing reconfigurable processor cores

A scheduler of a reconfigurable array, a method of scheduling commands, and a computing apparatus are provided. To perform a loop operation in a reconfigurable array, a recurrence node, a producer node, and a predecessor node are detected from a data flow graph of the loop operation such that resources are assigned to such nodes so as to increase the loop operating speed. Also, a dedicated path having a fixed delay may be added to the assigned resources.

Scheduler of reconfigurable array, method of scheduling commands, and computing apparatus

A processor simulation technique to evaluate the performance of a processor that executes application programs is provided. The processor simulation technique may be used to optimize the execution of an application program. A simulator of a reconfigurable processor including a plurality of functional units models a processor by representing routing paths between functional units that generate operands and functional units that consume the operands. The size of each queue may be decided based on information regarding routing delays between functional units and stage information of iteration loops according to modulo scheduling received from a scheduler. A modeling code DB that stores host-oriented binary codes for operations of routing queues is also provided. The simulation may be performed by executing a host-directed binary code corresponding to a binary file instead of the binary file.

Apparatus and method for simulating a reconfigurable processor

A computing apparatus for accessing a multiple bank memory is provided. The computing apparatus includes a processor, a memory and a memory controller which is configured to store data in a data buffer by accessing the memory in an aligned word unit and output, in response to a request for an unaligned memory access by the processor, requested data by extracting the request data from the data buffer.

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Seoul, South Korea

Tae-Wook Oh