Yonsei University

Qualcomm Incorporated

Tae Woo Oh

Seong Ook Jung

Se Keon Kim

Se Hee Lim

Dong Han Ko

Seong-Ook Jung

Hanwool Jeong

Stanley Seungchul Song

Periannan Chidambaram

Giridhar Nallapati

Ju Hyun Park

Han Wool Jeong

Exemplary embodiments provide a sensing amplifier based flip-flop applying a nonvolatile memory device which is applicable to a mobile device which has a small hardware area, uses a small control signal, does not include a separate write circuit, has low writing power consumption, a short reading time and small power consumption, and requires a low power operation.

Ferroelectric FET nonvolatile sense-amplifier-based flip-flop

A nonvolatile memory device according to the embodiment includes: a first inverter; and a second inverter cross-coupled to the first inverter, wherein the second inverter includes a pull-up transistor, a pull-down transistor, and a ferroelectric field effect transistor having gate nodes connected to each other, and a restore transistor having one electrode connected to the ferroelectric field effect transistor, and the second inverter stores data in a nonvolatile manner.

Nonvolatile memory device and latch including the same

A PUF apparatus comprises: a PUF cell array in which a plurality of PUF cells are arranged each including a FeFET pair whose gates are commonly connected to a corresponding word line among a plurality of word lines, and whose drains and sources are connected to a corresponding bit line pair and a corresponding source line pair among a plurality of bit line pairs and a plurality of source line pairs running in a direction crossing the plurality of word lines; and a read-write-back block which is activated according to a read enable signal, and senses and amplifies a voltage difference occurring in a corresponding bit line pair among the plurality of bit line pairs according to the difference in driving strength due to a deviation in a manufacturing process of the FeFET pair in the PUF cell selected by a selected word line among the plurality of word lines.

Physically unclonable function apparatus based on ferroelectric elements and operation method thereof

A ferroelectric random access memory device comprises: a memory cell array including a plurality of memory cells each having one ferroelectric transistor (FeFET) connected between a read line of a plurality of read lines and a source line of a plurality of source lines and one transistor connected between a bit line of a plurality of bit lines and a gate of the FeFET and having a gate connected to a corresponding word line of a plurality of word lines; and a read/write control unit, when address information for a memory cell to be written is applied with a write command and data, selecting a word line and a read line corresponding to a row address and applying a write voltage having a positive voltage level, and applying a ground voltage to the selected read line, and applying the write voltage to a bit line corresponding to a memory cell.

Ferroelectric random access memory device and method for operating read and write thereof

Disclosed is an SRAM cell capable of performing a differential operation. An SRAM cell according to an embodiment of the present disclosure may include a data node portion including four transistors constituting first and second data nodes; a data controller including first and second pass-gate transistors configured to control read and write of data in the first and second data nodes; and a control transistor connected to the data node portion through the second data node and configured to be controlled based on a driving voltage of a second word line having an opposite polarity to a first word line transmitting a driving voltage to the data controller.

Static random access memory cell capable of performing differential operation

Adaptive pulse generation circuits for clocking pulse latches with minimum hold time are provided. In one aspect, an adaptive pulse generation circuit employs a dynamic XOR-based logic gate configured to provide a pulse generation signal based on an XOR-based function of data input and data output-based signals of a pulse latch. A pull-down keeper circuit is configured to pull the pulse generation signal to a ground voltage in response to the pulse generation signal being in an inactive state while the clock signal is in an active state. A logic circuit is configured to generate an adaptive pulse signal to clock a pulse latch in response to the pulse generation signal and the clock signal being in an active state. This configuration results in the pulse width of the adaptive pulse signal corresponding to the input-to-output delay of the pulse latch.

Adaptive pulse generation circuits for clocking pulse latches with minimum hold time

Provided is a local bit line-sharing memory device, including a plurality of memory cells that share a local bit line pair; a pre-charging unit that is connected to a write bit line pair and pre-charges the local bit line pair; and a data reading unit that reads data when bit line voltage pre-charged in a memory cell selected from the memory cells is discharged.

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Seoul, South Korea

Tae Woo Oh