Applied Materials, Inc.

General Electric Company

Tae Won Kim

Marc Schaepkens

Min Yan

Dmitry Lubomirsky

Saravjeet Singh

Shashank C Deshmukh

Christian Maria Anton Heller

Ahmet Gun Erlat

Kyeong-Tae Lee

Soonam Park

Valentin Nikolov Todorow

Alexander Miller Paterson

Tien Fak Tan

Laksheswar Kalita

LokKee Loh

Anil Raj Duggal

Paul Alan McConnelee

Thomas Bert Gorczyca

Jennifer Y Sun

Suketu Arun Parikh

Jingchun Zhang

Toan Q Tran

Anisul Haque Khan

Xiaowei Wu

Xiao-Ming He

Valentin N Todorov

Stephen Yuen

Cheng-Hsuan Chou

Chirantha P Rodrigo

Tsz Keung Cheung

Satya Gowthami Achanta

Paul Alan Mcconnelee

Christian Maria Heller

Exemplary semiconductor processing chamber showerheads may include a dielectric plate characterized by a first surface and a second surface opposite the first surface. The dielectric plate may define a plurality of apertures through the dielectric plate. The dielectric plate may define a first annular channel in the first surface of the dielectric plate, and the first annular channel may extend about the plurality of apertures. The dielectric plate may define a second annular channel in the first surface of the dielectric plate. The second annular channel may be formed radially outward from the first annular channel. The showerheads may also include a conductive material embedded within the dielectric plate and extending about the plurality of apertures without being exposed by the apertures. The conductive material may be exposed at the second annular channel.

Ceramic showerheads with conductive electrodes

Exemplary etching methods may include flowing a hydrogen-containing precursor into a semiconductor processing chamber. The methods may include flowing a fluorine-containing precursor into a remote plasma region of the semiconductor processing chamber. The methods may include forming a plasma of the fluorine-containing precursor in the remote plasma region. The methods may include etching a pre-determined amount of a silicon-containing material from a substrate in a processing region of the semiconductor processing chamber. The methods may include measuring a radical density within the remote plasma region during the etching. The methods may also include halting the flow of the hydrogen-containing precursor into the semiconductor processing chamber when the radical density measured over time correlates to a produced amount of etchant to remove the pre-determined amount of the silicon-containing material.

Systems and methods for improved performance in semiconductor processing

A method of applying a multi-layer plasma resistant coating on an article comprises performing plating or ALD to form a conformal first plasma resistant layer on an article, wherein the conformal first plasma resistant layer is formed on a surface of the article and on walls of high aspect ratio features in the article. The conformal first plasma resistant coating has a porosity of approximately 0% and a thickness of approximately 200 nm to approximately 1 micron. One of electron beam ion assisted deposition (EB-IAD), plasma enhanced chemical vapor deposition (PECVD), aerosol deposition or plasma spraying is then performed to form a second plasma resistant layer that covers the conformal first plasma resistant layer at a region of the surface but not at the walls of the high aspect ratio features.

Multi-layer plasma erosion protection for chamber components

An inductively-coupled plasma processing chamber has a chamber with a ceiling. A first and second antenna are placed adjacent to the ceiling. The first antenna is concentric to the second antenna. A plasma source power supply is coupled to the first and second antenna. The plasma source power supply generates a first RF power to the first antenna, and a second RF power to the second antenna. A substrate support disposed within the chamber. The size of the first antenna and a distance between the substrate support are such that the etch rate of the substrate on the substrate support is substantially uniform.

Methods to eliminate 'M-shape' etch rate profile in inductively coupled plasma reactor

A composite article with at least one high integrity protective coating, the high integrity protective coating having at least one planarizing layer and at least one organic-inorganic composition barrier coating layer. A method for depositing a high integrity protective coating.

High integrity protective coatings

A barrier coating for a composite article is provided. The barrier coating includes an organic zone; an inorganic zone; and an interface zone between the organic zone and the inorganic zone.

Barrier coating and method

A barrier coating of organic-inorganic composition, the barrier coating having optical properties that are substantially uniform along an axis of light transmission, said axis oriented substantially perpendicular to the surface of the coating.

Barrier coatings

A pulsed plasma system with pulsed reaction gas replenish for etching semiconductor structures is described. In an embodiment, a portion of a sample is removed by applying a pulsed plasma etch process. The pulsed plasma etch process comprises a plurality of duty cycles, wherein each duty cycle represents the combination of an ON state and an OFF state of a plasma. The plasma is generated from a reaction gas, wherein the reaction gas is replenished during the OFF state of the plasma, but not during the ON state. In another embodiment, a first portion of a sample is removed by applying a continuous plasma etch process. The continuous plasma etch process is then terminated and a second portion of the sample is removed by applying a pulsed plasma etch process having pulsed reaction gas replenish.

Pulsed-plasma system with pulsed reaction gas replenish for etching semiconductors structures

A pulsed plasma system for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. The ON state of a duty cycle is of a duration sufficiently short to substantially inhibit micro-loading in a reaction region adjacent to the sample, while the OFF state of the duty cycle is of a duration sufficiently long to substantially enable removal of a set of etch by-products from the reaction region. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.

Pulsed-plasma system for etching semiconductor structures

A pulsed plasma system with pulsed sample bias for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. A negative bias is applied to the sample during the ON state of each duty cycle, while a zero bias is applied to the sample during the OFF state of each duty cycle. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.

Pulsed-plasma system with pulsed sample bias for etching semiconductor substrates

The invention relates to composite articles comprising a substrate and additional layers on the substrate. According to one example, the layers are selected so that the difference in the coefficient of thermal expansion (CTE) between the substrate and a first layer on one side of the substrate is substantially equal to the CTE difference between the substrate and a second layer on the other side of the substrate. The stress caused by the CTE difference and/or shrinkage on one side of the substrate during heating or cooling is balanced by the stress caused by the CTE difference on the other side of the substrate during heating or cooling. Such stress balancing can reduce or minimize curling of the substrate.

Multilayer device and method of making

Growing community of inventors

San Jose, CA, United States of America

Tae Won Kim