Samsung Electronics Co., Ltd.

Tae-won Ahn

Kyung-Suc Nah

A phase detector includes a Gilbert block for outputting a signal proportional to a phase difference between first and second input signals to a first output terminal, and a current source for determining a current in the first output terminal. The current source is controlled by a reference current signal. A converter outputs a current to a second output terminal in response to the signal output from the first output terminal. A variable current source varies the current output to the second output terminal. A controller controls the variable current source in response to the first and second input signals.

Phase detector for automatically controlling offset current and phase locked loop including the same

The present invention relates to a phase-locked loop (PLL) circuit and, more particularly to a PLL with a phase lock detection circuit. The PLL circuit includes a phase detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a frequency divider, and a phase lock detection circuit having two current charging/discharging circuits with first and second constant current sources for generating a phase lock signal having a pulse form through charging/discharging a capacitor. A voltage level of the capacitor is changed with a hysteresis characteristic. In the out-of-lock state of the PLL circuit, the discharging speed of the capacitor is faster than the charging speed thereof. In the phase lock state of the PLL circuit, the charging speed of the capacitor is faster than the discharging speed thereof. Since the charging/discharging operation of the capacitor is executed linearly and symmetrically, the phase lock detection circuit according to the present invention can obtain stable phase lock information. In addition, it is able to forecast the result of the phase lock state apart from a process variation by using the current mirror.

Phase lock detection circuit for phase-locked loop circuit

A phase lock detection circuit includes a phase detection circuit that produces a phase detect signal having one of a first logic state or a second logic state responsive to a first input signal and a second input signal applied thereto. A stabilized phase lock indication circuit is electrically coupled to the phase detection circuit and produces a phase lock indication signal having one of a first logic state or a second logic state, the phase lock indication signal changing to a respective one of its first and second logic states in response to the phase detect signal remaining in a respective one of its first and second logic states for a predetermined time interval. In a first embodiment, the phase lock indication is controlled by monitoring a digital count. In a second embodiment, the phase lock indication signal is controlled by monitoring a capacitor voltage. Related operating methods are also discussed.

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Seoul, South Korea

Tae-won Ahn