Skhynix Inc.

Hynix Semiconductor Inc.

Tae Su Jang

Min Soo Yoo

Sang Don Lee

Jung Ho Lee

Sung Woong Chung

Sung Joo Hong

Yong Taik Kim

Jeong Seob Kye

A semiconductor device that has a passing gate with a single gate electrode and a main gate with lower and upper gate electrodes mitigates gate induced drain leakage (GIDL). Additional elements that help mitigate GIDL include the upper gate electrode having a lower work function than the lower gate electrode, and the lower gate electrode being disposed below a storage node junction region while the upper gate electrode is disposed at a same level as the storage node junction region.

Semiconductor device having passing gate and method for fabricating the same

A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.

Semiconductor device and method for forming the same

An embodiment of the semiconductor device includes a recess formed in an active region, a gate buried in a lower part of the recess, a first capping insulation film formed over the gate, a second capping insulation film formed over the first capping insulation film, and a third capping insulation film formed over the second capping insulation film. In the semiconductor device including the buried gate, mechanical stress caused by a nitride film can be reduced by reducing the volume of a nitride film in a capping insulation film formed over a buried gate, and the ratio of silicon to nitrogen of the nitride film is adjusted, so that mechanical stress is reduced, resulting in improvement of operation characteristics of the semiconductor device.

Semiconductor device including buried gate, module and system, and method for manufacturing

According to a method of manufacturing a semiconductor device including a buried gate, after a recess is formed by etching a semiconductor substrate, since an etching back process is not performed on a gate electrode material buried within the recess, variability in the depth of the gate electrode material can be reduced. In addition, GIDL can be improved by a selective oxidation process and control of a thickness of a spacer and data retention time can be increased.

Method of manufacturing semiconductor device using an oxidation process to increase thickness of a gate insulation layer

An all around gate type semiconductor device improves mobility of electrons and holes by using a silicon germanium pillar and a silicon layer surrounding the silicon germanium pillar as a vertical channel. A gate electrode is formed to surround the vertical channel. When a semiconductor device is used as a nMOSFET, the silicon layer strained by silicon germanium is used as the channel to increase electron mobility. When the semiconductor device is used as a pMOSFET, the silicon germanium pillar is used as the channel to increase hole mobility. Thus, the semiconductor device can enhance current supply capacity regardless of transistor type.

All around gate type semiconductor device and method of manufacturing the same

A semiconductor device and a method for fabricating the same. A plurality of gate patterns are formed over a first-conductivity type silicon layer of a silicon-on-insulator semiconductor substrate including a buried insulation layer, so as to be separated from each other. A plurality of silicon bodies are formed under the gate patterns, by removing a portion of the first-conductivity type silicon layer exposed between the gate patterns. A plurality of polysilicon spacers are formed over a sidewall of the silicon bodies, and each contains a second-conductivity type dopant. A contact plug is electrically connected to at least one of the polysilicon spacers.

Semiconductor device and method for fabricating the same

A non-volatile semiconductor memory apparatus includes a first memory area configured to include a plurality of non-volatile memory cells, a second memory area configured to include a plurality of memory cells whose write speed is faster than the plurality of non-volatile memory cells, and a host interface configured to control the first and second memory areas, wherein the first and second memory areas are configured to be provided with the same address signal and command signal from the host interface.

Non-volatile semiconductor memory apparatus

An SOI device includes an SOI substrate having a structure in which a first buried oxide layer and a silicon layer are stacked in turn over a semiconductor substrate. A gate is formed over the silicon layer of the SOI substrate. A second buried oxide layer is formed at both sides of the gate in a lower portion of the silicon layer so that a lower end portion of the second buried oxide layer is in contact with the first buried oxide layer. A junction region is then formed in the portion of the silicon layer above the second buried oxide layer so that the lower end portion of the junction region is in contact with the second buried oxide layer.

Silicon on insulator device and method for fabricating the same

A method for manufacturing a semiconductor device that includes forming a pillar pattern including a sidewall contact over a semiconductor substrate; forming a silicon layer in a lower portion disposed between the pillar patterns; implanting ions into the silicon layer; diffusing the implanted impurity ions into the inside of the pillar pattern to form an ion-implanting region; removing the silicon layer; and burying a conductive material in the lower portion disposed between the pillar patterns. The method can prevent a floating body effect by adding a process of a vertical channel transistor.

Diffusing impurity ions into pillars to form vertical transistors

A semiconductor memory apparatus includes a unit cell with a transistor having a floated body and a capacitor for storing charges; a word line for activating the unit cell; and a bit line for transmitting data to the unit cell.

Semiconductor memory apparatus

Disclosed herein is a semiconductor memory device including plural unit cells, each constituted with a floating body transistor without any capacitor, to prevent data distortion and data crash in the unit cell. A semiconductor memory device comprises plural active regions and a device isolation layer for separating each active region from each others, wherein the plural active regions stand in row and column lines.

High integrated semiconductor memory device

A method for fabricating a semiconductor device comprises forming a deposition structure including a first substrate, an insulating layer and a second substrate of a SOI substrate; etching the second substrate located in a boundary of cell and core regions and a peripheral region to form a line-type trench; filling an isolating film in the trench; removing the second substrate and the insulating layer of the peripheral region; performing a selective epitaxial growth (SEG) process using the first substrate exposed in the peripheral region to form an epitaxial layer; and performing a chemical mechanical polishing (CMP) process on the epitaxial layer. As a result, the method has a floating body effect to shorten a developing period and improve a process yield.

A method of fabricating a semiconductor device includes forming an ion implanted region on a semiconductor substrate in a cell/core region. The semiconductor substrate is selectively etched to form a recess. The recess exposes a boundary of the ion implanted region. The ion implanted region exposed at the bottom of the recess is removed to form an under-cut space in the semiconductor substrate. An insulating film is formed to form a substrate having a silicon-on-insulator (SOI) structure in the cell/core region. The insulating film fills the under-cut space and the recess.

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Gwacheon, South Korea

Tae Su Jang