Samsung Electronics Co., Ltd.

Tae-Soo Park

Hyeon-Deok Lee

Kyung-Tae Lee

Young-sub You

Bong-hyun Kim

Yong-Woo Hyung

Young-Wug Kim

Jin-Won Jun

Heon-Heoung Leam

Disclosed is a method of manufacturing a MOS transistor having an enhanced reliability. A passivation layer is formed on a gate electrode and on a substrate to prevent a generation of a recess on the substrate. After a mask pattern is formed on the substrate for masking a portion of the substrate, impurities are implanted into an exposed portion of the substrate to form source and drain regions. The substrate is rinsed so that the passivation layer or a recess-prevention layer is substantially entirely or partially removed while the mask pattern is substantially completely removed, thereby forming the MOS transistor. Therefore, the generation of the recess in the source and drain region of the substrate can be prevented due to the passivation layer during rinsing of the substrate.

Method of manufacturing a metal oxide semiconductor transistor

A method of forming a dual damascene interconnection employs a low-k dielectric organic polymer as an insulating layer. With only one hard mask layer, ashing damage to the insulating layer is prevented using a hard mask layer and an etch-stop layer that are different in etch rate from that of a self-aligned spacer. Further, it is possible to form a via hole that is smaller than the resolution limit of the photolithographic process. As a result, the process is simplified and a photoresist tail phenomenon does not occur.

Method of forming dual damascene interconnection using low-k dielectric

Growing community of inventors

Gyeonggi-do, South Korea

Tae-Soo Park