Skhynix Inc.

Hynix Semiconductor Inc.

Sketchon Inc.

Tae Sik Yun

Sang Jin Byeon

Kang Seol Lee

Jong Chern Lee

Jong In Lee

Kyu Suk Lee

Dong Hwee Kim

Won Woong Seok

Hyung Dong Lee

Young Jun Ku

Chun Seok Jeong

Kee Teok Park

Jun Gi Choi

Heat Bit Park

Sang Hoon Shin

A Ram Rim

Dong Beom Lee

Sang Mook Oh

Dong Hoon Song

A semiconductor device includes a memory bank including a first memory block, a second memory block, and a redundancy memory block, and a column line selection circuit configured, when a fail occurs in a first column line of the first memory block, to replace the first column line of the first memory block with a first redundancy line of the redundancy memory block, and replace a second column line of the second memory block with a second redundancy line of the redundancy memory block.

Semiconductor device

Set of portable printer and docking station

A skin printing solution system includes a skin printing device that provides a user with a skin printing solution user interface including an online art gallery, a skin printing server that provides the online art gallery to the skin printing device, and a skin printer that outputs a tattoo image received from the skin printing device to a print region. Herein, when the user selects a tattoo image through the skin printing solution user interface, the skin printing device receives the selected tattoo image from the skin printing server and transmits the received tattoo image to the skin printer. In addition, the online art gallery includes multiple tattoo images, and the print region is the skin of the user or a different user.

Skin printing solution system, skin printing device, skin printer and image printing method therefor, image providing method and device therefor, and two-component ink for skin print and manufacturing method therefor

A memory system and a method for operating the same, wherein the memory system includes a first memory and a second memory each configured to store data. The memory system further includes a test and repair circuit operationally connected to the first memory and to the second memory. The test and repair circuit is configured to receive a test initiation signal and perform, in response to receiving the test initiation signal, a test operation on at least one of the first memory and the second memory. The test and repair circuit is also configured to perform, based on a result of the test operation, a repair operation on the at least one of the first memory and the second memory.

Memory system for improving memory reliability and memory management method for the same

A self-refresh control device may be provided. The self-refresh control device may include a refresh signal output circuit configured to generate self-refresh signals with an oscillator and provide a refresh signal. The self-refresh control device may begin a self-refresh mode in response to a clock enable signal and a self-refresh signal within a self-refresh entry period, and may prevent performance of a new self-refresh operation by delaying an additional self-refresh signal until after the self-refresh entry period has ended.

Self-refresh control device

A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

Semiconductor system having semiconductor apparatus and method of determining delay amount using the semiconductor apparatus

Various embodiments of a test mode control circuit of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, the test mode control circuit may include: a test mode control block configured to generate a plurality of control signal sets in response to a first address signal set and a second address signal set which are sequentially inputted; a test mode transfer block configured to transfer a plurality of test mode signals, which are generated according to a combination of the plurality of control signal sets, to a plurality of circuit blocks of the semiconductor apparatus; and a plurality of global lines configured to transmit the plurality of control signal sets to the test mode transfer block.

Test mode control circuit of semiconductor apparatus and control method thereof

A semiconductor apparatus is provided. The apparatus includes a transmission control unit configured to generate, in response to a received pulse signal having a first pulse width, transmission control signals with a second pulse width larger than the first pulse width and synchronization control signals with a third pulse width larger than the second pulse width. The apparatus also includes a reception control unit configured to generate reception control signals in response to the synchronization control signals.

Semiconductor apparatus for transmitting and receiving signals among a plurality of chips

Semiconductor apparatus

A refresh control circuit of a semiconductor apparatus includes a repair address processing unit configured to compare refresh addresses and repair information, activate a redundant enable signal, and convert the semiconductor apparatus into the same operation state as an initialization state of the repair information in response to activation of a repair initialization signal; a refresh counter configured to count the refresh addresses extended to a signal bit in response to activation of a redundant count enable signal; and a refresh control unit configured to activate the repair initialization signal and the redundant count enable signal when an additional refresh mode is set in response to a refresh command.

Refresh control circuit of semiconductor apparatus and refresh method using the same

A sub word line driver and a semiconductor integrated circuit device having the same are provided. The semiconductor integrated circuit device includes adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word line drivers of adjacent sub word line drivers share one keeper transistor with each other, and third and fourth sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other.

Sub word line driver and semiconductor integrated circuit device

A semiconductor memory device selects one of a plurality of memory cells as a dummy memory cell. The dummy memory cell is connected to a bit line that is complementary to a bit line connected to a selected memory cell. This technique advantageously compensates capacitance of the bit line. The semiconductor memory device comprises a selected memory cell connected to a first bit line and a first word line, a dummy memory cell connected to a second bit line complementary to the first bit line and a second word line, and a sense amplifier connected to the first and second bit lines and configured to read data stored in the selected memory cell by simultaneously enablement of the first and second word lines.

Semiconductor memory device

A semiconductor apparatus with an open bit line structure includes a memory bank including a plurality of memory cell blocks and dummy mats, in which a plurality of bit lines are formed, a bit line sense amplifier configured to be arranged between the plurality of memory cell blocks and the dummy mats, compare a voltage difference between a bit line and a complementary bit line, and amplify the difference, and a dummy word line driving unit configured to selectively activate a dummy word line of the dummy mat in response to a test mode.

Semiconductor apparatus with open bit line structure

Various embodiments of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a chip, scribe lanes disposed around the chip, and a probe test logic circuit for conducting a probe test on the chip. The probe test logic circuit is disposed on a portion of the scribe lanes.

Growing community of inventors

Ichon-shi, South Korea

Tae Sik Yun