Hynix Semiconductor Inc.

Skhynix Inc.

Samsung Electronics Co., Ltd.

Tae-Sik Yun

Kang-Seol Lee

Sung-Chul Park

Young-Jun Ku

Sang-Mook Oh

Yong-Lim Go

Hyunjoon Kim

Jae-Jin Lee

Seok-Cheol Yoon

Jae-Bum Ko

Jung-Min Park

Kee-Teok Park

Dae-Suk Kim

Soon-Ho Hwang

No-Guen Joo

Kyu-suk Lee

Hyun-Woo Kang

Dong-Beom Lee

Kunhyung Lee

Hyeogki Kim

Byung-Koog Ra

KiDoo Kim

Kwang-Mo Yang

Nam-Ung Kim

The present invention relates to an electronic device and, more particularly, to an electronic device and a method for transmitting and receiving signals. To this end, the electronic device according to the present invention may comprise: a transceiving unit comprising a first group of power amplifiers (PAs) including at least one PA and a second group of PAs including at least one PA; an antenna unit comprising a first antenna selectively coupled to a PA supporting a first frequency range or a second frequency range of the first group of PAs and the second group of the PAs, and a second antenna selectively coupled to a PA supporting the second frequency range or a third frequency range of the first group of PAs and the second group of the PAs; a power supply unit comprising a first power supply modulator connected to the first group of PAs and a second power supply modulator connected to the second group of PAs; and a communication processor for changing an output voltage at least in part on the basis of transmit power of the PA coupled to at least one of the first power supply modulator and the second power supply modulator, wherein at least one of the first group of PAs and at least one of the second group of PAs are capable of transmitting signals simultaneously.

Electronic device and method for transmitting and receiving signals

A semiconductor memory device includes: a plurality of banks each including a plurality of cell mats and a plurality of sense amplifiers shared by adjacent cell mats; and a bank control circuit suitable for activating a normal word line of a particular cell mat of a bank selected according to a refresh command including bank information, and activating a target word line of a cell mat that does not share a sense amplifier with the particular cell mat according to a target refresh command after a preset delay time.

Semiconductor memory device and operating method thereof

A mobile image forming apparatus and an image compensation method of the mobile image forming apparatus are provided. The mobile image forming apparatus includes a surface measurer configured to measure an area touched by the mobile image forming apparatus among a surface area on which a print image is to be printed, an image processor configured to retrieve at least one of curvature data and moisture data from the measured result, and compensate the print image based on the at least one of the curvature data and moisture data retrieved, and an image former configured to print the compensated print image on the surface.

Mobile image forming apparatus, image compensation method thereof and non-transitory computer readable recording medium

A memory device may include a plurality of first sense amplifiers including a plurality of corresponding first input terminals, a plurality of second sense amplifiers including a plurality of corresponding second input terminals, the plurality of first and second sense amplifiers being suitable for amplifying data received through the respective plurality of first and second input terminals, and for outputting the amplified data which include first and second data outputted by the plurality of first sense amplifiers and third and fourth data outputted by the plurality of second sense amplifiers; a plurality of first pipe latches suitable for latching and outputting the first and second data at a specific interval; a plurality of second pipe latches suitable for latching and outputting the third and fourth data at a specific interval; and an input/output line coupled to the plurality of first and second pipe latches, suitable for outputting the first, second, third and fourth data.

Memory device with sense amplifier groups and pipe latch groups

A semiconductor device may include: a plurality of output paths, which include a plurality of through silicon vias (TSVs), respectively, and suitable for transmission of test confirmation information; an information provider suitable for providing the test confirmation information to the plurality of TSVs; and an output controller suitable for selectively blocking one of the output paths including a failed one among the plurality of TSVs.

Semiconductor device for verifying operation of through silicon vias

A repair circuit includes a normal decoder suitable for decoding partial input addresses of input addresses in response to a first control signal, a comparison unit suitable for comparing the partial input addresses and partial repair addresses of repair addresses in response to a second control signal, and generating a column repair signal when the partial input addresses and the partial repair addresses correspond to each other, and a redundancy decoder suitable for decoding the repair addresses in response to the column repair signal.

Repair circuit and semiconductor memory device including the same

A circuit of a semiconductor memory device may include a delay unit suitable for delaying a column pulse signal, and sequentially generating a first strobe source signal, a column source signal, and a second strobe source signal at a predetermined time interval, and an input/output strobe signal generation unit suitable for generating an input/output strobe signal which is activated during a period in which both of the first and second strobe source signals are activated.

Semiconductor memory device

A semiconductor memory device includes a first pre-charge control block suitable for generating a first control signal by counting a number of toggles of an operation clock in response to a first active pulse in a self-refresh operation exit mode, a second pre-charge control block suitable for generating a second control signal in response to an active command for an active operation in a self-refresh operation mode, and an operation control block suitable for disabling the first pre-charge control block in the self-refresh operation mode, and disabling the second pre-charge control block in a self-refresh operation exit mode, wherein a pre-charge operation starts in response to the first and second control signals after the active operation. The semiconductor memory device may then be secured in a minimal time for stably performing an active operation during a self-refresh operation.

Semiconductor memory device and method for operating the same

A signal transmission/reception system includes a transmission line, a signal transmission circuit configured to generate a transfer signal and transfer the transfer signal through the transmission line, wherein a logic value of the transfer signal is changed whenever a pulse signal is input to the signal transmission circuit, and a signal reception circuit configured to receive the transfer signal through the transmission line and generate a restoration signal using the transfer signal and a delayed transfer signal obtained by delaying the transfer signal.

Signal transmission/reception system

A semiconductor integrated circuit includes: a normal fuse cell array programmed with a normal fuse data; a dummy fuse cell array programmed with a verifying fuse data; and a sensor configured to read the verifying fuse data from the dummy fuse cell array and read the normal fuse data from the normal fuse cell array, wherein the normal fuse cell array is configured to be read according to a reading result of the dummy fuse cell array.

Semiconductor integrated circuit having array E-fuse and driving method thereof

A substrate transfer container comprises a housing including a plurality of substrate slots positioned within a gas chamber having an interior environment. Each substrate slot accommodates a substrate undergoing a substrate manufacturing process, the interior environment of the gas chamber being selectively sealed from an exterior environment. A detection unit at the housing is constructed and arranged to detect an environmental property of the interior environment of the gas chamber, and to generate a detection signal in response. A signal transmission module at the housing is configured to wirelessly transmit a detection signal received from the detection unit.

Substrate transfer container, gas purge monitoring tool, and semiconductor manufacturing equipment with the same

A semiconductor integrated circuit includes a first semiconductor chip including a first output circuit which is enabled in a first operation mode and outputs a first output signal and a second output circuit which is enabled in a second operation mode and outputs a second output signal; a second semiconductor chip including a first input circuit which is enabled in the first operation mode and receives the first output signal and a second input circuit which is enabled in the second operation mode and receives the second output signal; and a common through chip via arranged to vertically penetrate through the semiconductor chip, be coupled with the first and second output circuits in one end and coupled with the first and second input circuits in the other end, and interface transfer of the first and second output signals which are enabled in different operation modes, including the first and second operation modes.

Semiconductor integrated circuit having stacked semiconductor chips and vias therebetween

Disclosed is a semiconductor memory apparatus which improves the time to transmit write data to a memory cell and improves data retention time of the memory cell. To this end, the semiconductor memory apparatus includes a bit-line sense amplifier that senses and amplifies data of bit-line pairs by driving power supplied through a pull up power line and a pull down power line and transmits the amplified data to a memory cell. A bit-line sense amplification power supply unit supplies pull up driving voltage and pull down driving voltage to the pull up and pull down power lines in an active mode and supplies an over driving voltage and the pull down driving voltage having a higher voltage level than the pull up driving voltage to the pull up and pull down power lines until the memory cell is deactivated in a precharge mode.

Semiconductor memory apparatus and method of driving bit-line sense amplifier

A semiconductor memory device includes a cell block including a first bit line, a sense amplifier unit including a second bit line and configured to amplify a data signal applied to the second bit line, a connection unit configured to selectively connect the first bit line and the second bit line, a connection control unit configured to receive a control signal for driving the sense amplifier unit and a selection signal for selecting the cell block and generate a connection signal for activating the connection unit at a first time, and a sense amplifier driving control unit configured to receive the control signal and generate a sense amplifier driving signal for driving the sense amplifier unit at a second time after the first time.

Growing community of inventors

Gyeonggi-do, South Korea

Tae-Sik Yun