Texas Instruments Corporation

Other

Tae S Kim

Han-Tzong Yuan

Donald L Plumton

Francis Gabriel Celii

Jau-Yuann Yang

Simon Joshua Jacobs

Changming Jin

Gregory Boyd Shinn

Jin Zhao

Ju-Ai Ruan

Nathan J Kruse

August J Fischer

Ralf B Willecke

Mark R Visokay

Mahalingam Nandakumar

Bruce E Gnade

Chih-Chen Cho

Abbas Ali

Walter Marvin Duncan

Scott William Jessen

Makarand Ramkrishna Kulkarni

Francis J Morris

Yasushiro Nishioka

Sameer Kumar Ajmera

Sopa Chevacharoenkul

Steven Lee Prins

Erich Wesley Kinder

Satyavolu Papa Rao

Anand J Reddy

Hung-Yu Liu

Eric D Rullan

Donald L Plumpton

Can Duan

A method of fabricating an integrated circuit (IC) includes forming a dielectric layer on a substrate having a plurality of the IC. A thin-film resistor (TFR) layer is deposited on the dielectric layer, and an underlayer (UL) including carbon is formed on the TFR layer. A hard mask layer including silicon is formed on the UL. Masked etching of the hard mask layer transfers a pattern of a photoresist layer onto the hard mask layer to form a hard mask layer pattern. Masked etching of the UL transfers the hard mask layer pattern onto the UL to form a UL pattern. Masked etching of the TFR layer transfers the UL pattern onto the TFR layer to form a TFR layer pattern including a matched pair of TFRs. The matched pair of TFRs are generally included in circuitry configured together for implementing at least one function.

IC with matched thin film resistors

A method of assembling a flip chip IC package includes applying core underfill material to a surface of a package substrate in a pattern including an area corresponding to a core region of an IC die thereon that is to be attached, that excludes of an area corresponding to corners of the IC die. The IC die is bonded to the package substrate by pushing the IC die with a sufficient force for the core underfill material is displaced laterally by the bumps so that the bumps contact the land pads. After the pushing the corners of the IC die are not on the core underfill. Edge underfilling includes dispensing a second underfill material that is curable liquid to fill an area under the corners of the IC die. The second underfill material is cured resulting in it having a higher fracture strength as compared to the core underfill.

Multiple underfills for flip chip packages

In some embodiments, a method includes selecting, a first circuit layout, where the first circuit layout includes a circuit element representation, a design rule, and a target circuit element value. The method further includes receiving a plurality of circuit element values of circuit elements fabricated in each of multiple fabrication facilities using the design rule. The method also includes selecting a fabrication facility and a circuit element value of circuit elements fabricated in the selected fabrication facility using the design rule. Further the method includes determining a circuit element value calculation based on the selected circuit element values, and determining an adjustment value. This adjustment value is further used to customize the design rule. The method then includes generating a second circuit layout comprising the customized design rule, causing the fabrication facility to fabricate a circuit using the second circuit layout.

Customizing circuit layout design rules for fabrication facilities

A method of limiting plasma charging damage on ICs. A die includes gate stacks on active areas defined by a field dielectric. A pre-metal dielectric (PMD) layer is over the gate electrode. A contact masking material pattern is defined on the PMD layer including first contact defining features for forming active contacts and second contact defining features for forming dummy contacts (DC's) including over active areas and gate electrodes. Contacts are etched through the PMD layer using the contact masking material pattern to form active contacts and DC's. A patterned metal 1 (M1) layer is formed including first M1 portions over the active contacts and dummy M1 portions over the DC's. Metallization processing follows including forming interconnects so that the active contacts are connected to MOS transistors on the IC, and the DC's are not electrically connected to the MOS transistors.

Dummy contacts to mitigate plasma charging damage to gate dielectrics

An integrated circuit may include dual damascene interconnects formed using a via-first dual damascene process or a trench-first dual damascene process. The via-first process may be a partial-via-first process or a full-via-first process. A trench mask for a wide interconnect line which is at least twice as wide as a dual damascene via in the wide interconnect line may have a dielectric slot adjacent to the dual damascene via. The dual damascene via is laterally separated from the dielectric slot by no more than half a width of the dual damascene via.

Use of dielectric slots for reducing via resistance in dual damascene process

A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.

Semiconductor device manufactured by reducing hillock formation in metal interconnects

One aspect of the invention provides a method of forming a semiconductor device (). One aspect includes forming transistors () on a semiconductor substrate (), forming a first interlevel dielectric layer () over the transistors (), and forming metal interconnects () within the first interlevel dielectric layer (). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer () over the metal interconnects () and the first interlevel dielectric layer () within a deposition tool. An adhesion layer () is formed on the SiCN layer (), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer () is formed over the adhesion layer ().

Semiconductor device having improved adhesion and reduced blistering between etch stop layer and dielectric layer

A method of forming a film stack in an integrated circuit, said method comprising depositing a layer of silicon carbide adjacent a first layer of dielectric material, depositing a layer of silicon nitride adjacent the layer of silicon carbide, and depositing a second layer of dielectric material adjacent the layer of silicon nitride.

Bi-layer etch stop process for defect reduction and via stress migration improvement

An optocoupler structure comprising a semiconductor chip having an integrated circuit and an optically transparent, electrically insulating layer having first and second surfaces; an organic diode integral with said first surface, said diode operable to emit electromagnetic radiation; and said circuit including a radiation-sensitive semiconductor device integral with said second surface, electrically isolated from said diode, and positioned in the path of said radiation.

Optocouplers having integrated organic light-emitting diodes

A method of photolithographically patterning an organic semiconductor device, comprising the steps of protecting the organic layer of the device by depositing a metal layer thereon, depositing and patterning a photoresist layer on said metal layer, and selectively etching the exposed areas to pattern said metal layer and said organic layer. Specifically, the disclosed method provides the photolithographic fabrication of organic light emitting diodes (OLEDs) and organic lasers diodes (OLDs).

Photolithographic method for fabricating organic light-emitting diodes

A method and apparatus are disclosed for achieving a desired thickness profile in a semiconductor device ( ) using a flow-flange reactor ( ), by adjusting input flow ratios in the flow-flange ( ) of the reactor ( ). A target thickness profile is established. A first set of optimum input flow ratios are then determined in response to the target thickness profile, based upon a first plurality of sample thickness profiles and a first plurality of sets of sample input flow ratios, wherein each of the sample thickness profiles corresponds to one of the first plurality of sets of sample input flow ratios. The input flow ratios of the reactor ( ) are then adjusted in response to the first optimum set of input flow ratios.

Method and apparatus for achieving a desired thickness profile in a flow-flange reactor

A vertical field effect transistor (,) and fabrication method with buried gates (,) having gate sidewall crystal orientation the same as the substrate surface and a low index substrate crystal orientation without tilt to a higher index direction. The gate (,) may have modulated doping along the channel (,), and the drain (,) may have a lighter doping level than the channel which may be accomplished by an epitaxial overgrowth of the gates (,) to form the channels (,).

Epitaxial overgrowth method and devices

A vertical transistor (70) comprising a first semiconductor layer (14) of a first conductive type. A gate structure (32) of a second conductive type disposed on the first semiconductor layer (14). The gate structure (32) may include a plurality of gates (38) separated by channels (40). A second semiconductor layer (50) of the first conductive type may be disposed over the gate structure (32) and in the channels (40). An arresting element (36) may be disposed between and upper surface of the gates (38) and the second semiconductor layer (50). A void (52) may be formed in the second semiconductor layer (50) over the gate (38).

Growing community of inventors

Dallas, TX, United States of America

Tae S Kim