Samsung Electronics Co., Ltd.

Tae-Ouk Kwon

Seok-Hoon Kim

Sang-Bom Kang

Jung-Geun Jee

Hyun-jung Lee

Woo-Sung Lee

Su-Jin Shin

Chung-Geun Koh

Kwan-Yong Lim

Byeong-Chan Lee

Bon-Young Koo

Young-Pil Kim

Su-Jin Jung

Ui-hui Kwon

A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern.

Non-volatile memory devices and methods of manufacturing the same

Provided is a semiconductor device. The semiconductor device includes a fin on a substrate; a gate electrode cross the fin on the substrate; a source/drain formed on at least one of both sides of the gate electrode, and including a first film and a second film; and a stress film arranged between an isolation film on the substrate and the source/drain, and formed on a side surface of the fin.

Semiconductor device having a stress film on a side surface of a fin

A semiconductor device is formed with a gate pattern formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate at one side of the gate pattern. The semiconductor device can have a reduced leakage current and improved channel conductivity.

Method for manufacturing semiconductor device

A method of forming a transistor induces stress in the channel region using a stress memorization technique (SMT). Impurities are implanted into a substrate adjacent a gate electrode structure to produce an amorphous region adjacent the channel region. The amorphous region is then recrystallized by forming a metal-oxide layer over the amorphous region, and then thermally treating the same. The crystallization creates compressive stress in the amorphous region. As a result, stress is induced in the channel region of the substrate located under the gate electrode structure.

Methods of forming transistors and CMOS semiconductor devices using an SMT technique

Growing community of inventors

Hwaseong-si, South Korea

Tae-Ouk Kwon