Applied Materials, Inc.

Applied Komatsu Technology, Inc.

Patterson + Sheridan Llp

Tae Kyung Won

Soo Young Choi

John M White

Beom Soo Park

Dong-Kil Yim

Sanjay D Yadav

Shinichi Kurita

Suhail Anwar

Chien-Teh Kao

Seon-Mee Cho

Qunhua Wang

Robin L Tiner

Carl A Sorensen

Yi Cui

Li Hou

Ki Woon Kim

Gaku Furuta

William Reid Harshbarger

Shuran Sheng

Takako Takehara

Shouqian Shao

Xuena Zhang

Liwei Li

Jriyan Jerry Chen

Young Dong Lee

Jianhua Zhou

Quanyuan Shang

Robert Z Bachrach

Jrjyan Jerry Chen

Jozef Kudela

Yong Kee Chae

Dong Kil Yim

Young Eun Lee

Ya-Tang Yang

Jose Manuel Dieguez Campo

Eric Andrew Englhardt

Kam S Law

Wendell T Blonigan

Xiangxin Rui

David Tanner

Lai Zhao

Robert M Robertson

Dapeng Wang

Danny Cam Toan Lu

Jeffrey S Sullivan

Yacov Elgar

Asaf Schlezinger

Yujia Zhai

Harvey You

Stephen P Murphy

Jun Li

Wan-Yu Lin

James Craig Hunter

Helinda Nominanda

Charles Gay

Robert I Greene

Rodney Shunleong Lim

Penchala N Kankanala

Young Jin Choi

Fang Mei

Wenqing Dai

Parris Hawkins

Yong-Kee Chae

Nicholas G J De Vries

Tzay-Fa (Jeff) Su

Michel Ranjit Frei

Yun-chu Tsai

Won Ho Sung

Teresa Trowbridge

Hsiao-Lin Yang

Brice Walker

Hao-Chien Hsu

Yixuan Wu

Surendra Kanimihally Setty

Jung-Chi (Eric) Lu

Choi (Gene) Ho

Wing Hoo (Hendrick) Lo

Srujal (Steve) Patel

Matthew J B Saunders

Embodiments of the present disclosure generally relate to a lid suitable for use in a semiconductor processing chamber. The lid includes a plurality of dielectric windows coupled to a perforated faceplate. The lid also includes a plurality of support members coupled to the perforated faceplate and positioned between adjacent dielectric windows. The lid further includes a plurality inductive couplers. One or more of the inductive couplers includes a first lower portion, a second lower portion, and a bridge. The bridge is disposed over at least one of the plurality of support members. The first lower portion is positioned on a first dielectric window of the plurality of dielectric windows. The second lower portion is positioned on a second dielectric window of the plurality of dielectric windows. The second dielectric window is adjacent to the first dielectric window.

Multi-antenna unit for large area inductively coupled plasma processing apparatus

Embodiments of the present disclosure include methods and apparatus for depositing a plurality of layers on a large area substrate. In one embodiment, a processing chamber for plasma deposition is provided. The processing chamber includes a showerhead and a substrate support assembly. The showerhead is coupled to an RF power source and a ground and includes a plurality of perforated gas diffusion members. A plurality of plasma applicators is disposed within the showerhead, wherein one plasma applicator of the plurality of plasma applicators corresponds to one of the plurality of perforated gas diffusion members. Further, a DC bias power source is coupled to a substrate support assembly.

Film stress control for plasma enhanced chemical vapor deposition

Techniques are disclosed for methods of post-treating an etch stop or a passivation layer in a thin film transistor to increase the stability behavior of the thin film transistor.

Plasma treatment on metal-oxide TFT

In one implementation, a method for cleaning a processing chamber is provided. The method comprises introducing a reactive species into a processing chamber having a residual high-k dielectric material formed on one or more interior surfaces of the processing chamber. The reactive species is formed from a halogen-containing gas mixture and the one or more interior surfaces include at least one surface having a coating material formed thereon. The method further comprises reacting the residual high-k dielectric material with the reactive species to form a volatile product. The method further comprises removing the volatile product from the processing chamber. The removal rate of the residual high-k dielectric material is greater than a removal rate of the coating material. The high-k dielectric material is selected from zirconium dioxide (ZrO) and hafnium dioxide (HfO). The coating material includes a compound selected from alumina (AlO), yttrium-containing compounds, and combinations thereof.

Selective in-situ cleaning of high-k films from processing chamber using reactive gas precursor

Embodiments of the disclosure include methods and apparatus for electrostatically coupling a mask to a substrate support in a deposition chamber. In one embodiment, a substrate support is disclosed that includes a substrate receiving surface, a recessed portion disposed about a periphery of the substrate receiving surface, an electrostatic chuck disposed below the substrate receiving surface, and a plurality of compressible buttons disposed within a respective opening formed in the recessed portion that form an electrical circuit with the electrostatic chuck.

Substrate support for chucking of mask for deposition processes

Embodiments described herein relate to methods of tuning within semiconductor processes to improve plasma stability. In these embodiments, multiple matching networks are provided. Each of the matching networks couple a radio frequency (RF) source to one of multiple connection points located on an electrode. Based on tuning parameter information and physical geometry information, a controller determines a tuning sequence for the multiple matching networks. As such, some of the matching networks are tuned while the other matching networks are locked. Using multiple matching networks leads to a more uniform plasma within the process volume of the process chamber. Improved plasma uniformity leads to less substrate defects and better device performance. Additionally, in these embodiments, the ability to tune each of the matching networks in a sequence decreases or prevents interference from occurring between the matching networks.

Methods of tuning to improve plasma stability

A method of encapsulating an organic light emitting diode (OLED) is provided. The method includes generating a first plasma in a process chamber, the first plasma having an electron density of at least 10cmwhen an OLED device is positioned within the process chamber. The OLED device includes a substrate and an OLED formed on the substrate. The method further includes pretreating one or more surfaces of the OLED and substrate with the first plasma; depositing a first barrier layer comprising silicon and nitrogen over the OLED by generating a second plasma comprising silicon and nitrogen in the process chamber, the second plasma having an electron density of at least 10cm, and depositing a buffer layer over the first barrier layer; and depositing a second barrier layer comprising silicon and nitrogen over the buffer layer by generating a third plasma comprising silicon and nitrogen in the process chamber.

Thin-film encapsulation

The present disclosure relates to a chemical vapor deposition system for processing large area substrates. The chemical vapor deposition system includes a chemical vapor deposition chamber comprising a chamber body having a plurality of sidewalls, a lid assembly, and a bottom. A substrate support extends upward from the bottom within the chamber body. A gas distribution plate is located within the lid assembly. One or more cleaning gas injector ports coupled to corresponding one or more inlets in the plurality of sidewalls. Each of the one or more cleaning gas injector ports has a substantially oval-shaped or circular-shaped cleaning gas nozzle configured to provide reactive species from a remote plasma source to clean an underside of the gas distribution plate.

Remote plasma source cleaning nozzle for cleaning a gas distribution plate

Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.

Interface engineering for high capacitance capacitor for liquid crystal display

Embodiments of the present disclosure generally describe a method for depositing a barrier layer of SiN using a high density plasma chemical vapor deposition (HDP-CVD) process, and in particular, controlling a film stress of the deposited SiN layer by biasing the substrate during the deposition process.

CVD thin film stress control method for display application

Embodiments of a method of depositing a thin film on a substrate is provided that includes placing a substrate on a substrate support that is mounted in a processing region of a processing chamber, flowing a process fluid through a plurality of gas passages in a diffuser plate toward the substrate supported on the substrate support, wherein the diffuser plate has an upstream side and a downstream side and the downstream side has a substantially concave curvature, and each of the gas passages are formed between the upstream side and the downstream side, and creating a plasma between the downstream side of the diffuser plate and the substrate support.

Plasma uniformity control by gas diffuser hole design

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San Jose, CA, United States of America

Tae Kyung Won