Skhynix Inc.

Hynix Semiconductor Inc.

Tae Kyung Kim

Kun Young Lee

Dae Sung Eom

Hyoung Soon Yune

Tae Gyun Kim

Hyo Sub Yeom

Hyun Yul Kwon

Jeong Yun Lee

Chul Young Park

Jae Yoon Noh

Jik Ho Cho

Cheol Mo Jeong

Min Hee Jang

Woo Yung Jung

Sung Deok Kim

Eun Soo Kim

Choon Kun Ryu

Sung Soon Kim

Myung Kyu Ahn

Jung Myoung Shim

Yong Chul Shin

Woo Duck Jung

There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers, which are stacked in an alternating manner; at least one support structure penetrating the stack structure in a substantially vertical manner, the at least one support structure being formed in a contact region; and a contact plug penetrating the stack structure in a substantially vertical manner, the contact plug being formed in the contact region, the contact plug being connected to a contact pad that is disposed on the bottom of the stack structure. The at least one support structure is formed of an oxide layer.

Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

Manufacturing method of a semiconductor memory device

The semiconductor memory device includes: a first substrate including a peripheral circuit, first conductive contact patterns connected to the peripheral circuit, and a first upper insulating layer having grooves exposing the first conductive contact patterns; a second substrate including a memory cell array, a second upper insulating layer disposed on the memory cell array, the second upper insulating layer formed between the memory cell array and the first upper insulating layer, second conductive contact patterns protruding through the second upper insulating layer into an opening of the grooves; and conductive adhesive patterns filling the grooves to connect the second conductive contact patterns to the first conductive contact patterns.

Semiconductor memory device and method of manufacturing the same

A semiconductor device may include a first pattern. The semiconductor device may include a second pattern intersecting with the first pattern and including an intersection region with the first pattern and a non-intersection region.

Semiconductor device and method of manufacturing the same

The present disclosure relates to a semiconductor memory, device and a method of forming a semiconductor memory device. The method of manufacturing a semiconductor memory device, includes forming a tunnel insulation layer and a floating gate on a semiconductor substrate of an active region, forming a trench in the semiconductor substrate of an isolation region, forming, in the trench, a sacrificial layer having an upper surface positioned higher than a surface of the semiconductor substrate, forming a capping layer over the sacrificial layer, and forming an air gap by removing the sacrificial layer without removing the capping layer.

Semiconductor memory device and manufacturing method thereof

A semiconductor device includes interlayer insulating films spaced apart from each other and stacked over each other, and wherein first ends of the interlayer insulating films form a stepped structure; a slit penetrating the interlayer insulating films and dividing the interlayer insulating films into a plurality of stack structures; line patterns arranged between adjacent interlayer insulating films and separated from each other by the slit; pad patterns connected to the line patterns, formed over the first ends of the interlayer insulating films, and separated from each other by the slit; and at least one punch prevention pattern formed over sidewalls of the pad patterns adjacent to the slit and formed over the first ends of the interlayer insulating films.

Provided is a semiconductor device including a plurality of pillar columns, each of the plurality of pillar columns including a plurality of pillars arranged in one direction to be offset from each other, wherein an mth pillar and an (m+1)th pillar, among the plurality of pillars included in each pillar column, are aligned with each other (m is an integer of 0 or more).

Semiconductor device

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a core insulating film, a channel film surrounding the core insulating film and extending to a higher level than an upper surface of the core insulating film to have a first end of the channel film exposed over the core insulating film, a channel pad formed over an inner wall of the first end of the channel film exposed over the core insulating film, and a contact plug coupled to the channel pad.

A three-dimensional nonvolatile memory device includes a first vertical channel layer and a second vertical channel layer extending from a substrate, a plurality of memory cells, first selection transistors and second selection transistors spaced apart from each other along the first vertical channel layer and the second vertical channel layer, a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, and a common source line formed over the second vertical channel layer.

Three-dimensional nonvolatile memory device, semiconductor system including the same, and method of manufacturing the same

A semiconductor memory device includes a plurality of auxiliary patterns formed over a semiconductor substrate, a plurality of gate line patterns disposed in parallel with one another over the semiconductor substrate between the plurality of auxiliary patterns, and an air gap formed between the plurality of gate line patterns and between each of the plurality of gate line patterns and each of the auxiliary patterns.

Growing community of inventors

Chungcheongbuk-do, South Korea

Tae Kyung Kim