Lg Innotek Co., Ltd.

Amkor Technology, Inc.

Tae Ki Kim

Byong Jin Kim

Gi Jeong Kim

Yong Suk Kim

Ji Young Chung

Dong Keun Lee

Jae Min Bae

Won Bae Bang

Jin Seok Lee

Hyung Il Jeon

Hye Jin Jo

Yong Han Jeon

Il Sik Nam

A printed circuit board according to an embodiment includes an insulating layer; a first pad disposed on an upper surface of the insulating layer; a second pad disposed on a lower surface of the insulating layer; a first device mounted on the first pad; a second device mounted on the second pad; a first molding layer disposed on the insulating layer and molding the first device; and a second molding layer disposed on the lower surface of the insulating layer and molding the second device, wherein a lower surface of the second molding layer is positioned on the same plane as a lower surface of the second device.

Printed circuit board

A circuit board according to an embodiment includes an insulating layer; a circuit pattern disposed on an upper surface of the insulating layer; a first solder resist disposed on an upper surface of the insulating layer and having a height smaller than a height of the circuit pattern; and a second solder resist disposed on an upper surface of the first solder resist and including a first portion having an upper surface lower than an upper surface of the circuit pattern and a second portion having an upper surface higher than the upper surface of the circuit pattern, wherein the circuit pattern includes: a plurality of first circuit patterns disposed on an upper surface of a first region of the insulating layer, and a plurality of second circuit patterns disposed on an upper surface of a second region of the insulating layer; wherein the first portion of the second solder resist is disposed between the plurality of first circuit patterns to have an upper surface lower than an upper surface of the first circuit pattern; and wherein the second portion of the second solder resist has an upper surface higher than an upper surface of the second circuit pattern, and is disposed to cover the plurality of second circuit patterns between the plurality of second circuit patterns.

Circuit board

In one embodiment, an electronic package includes a substrate having a die pad plurality of lands embedded within substrate encapsulant. An electronic chip including an electronic component is connected to the die pad. The die pad is configured with a recessed well extending from a top surface of the die pad towards a bottom surface of the die pad. The electronic component is position at least proximate to and overlapping the recessed well to increase the distance between the die pad and the electronic component. In one embodiment, the electronic component includes a passive component, such as an inductor. A package body encapsulates the electronic chip and top surfaces of the substrate, and is further disposed within the recessed well. The die pad bottom surface is continuous below the recessed well.

Packaged electronic device having reduced parasitic effects and method

In one embodiment, a semiconductor device includes a single layer substrate having an insulation layer and conductive patterns on a first surface of the insulation layer. A semiconductor die is attached on a first surface of the single layer substrate and electrically connected to the conductive patterns. Conductive bumps are also on the first surface of the single layer substrate and electrically connected to the semiconductor die through the conductive patterns. An encapsulant overlaps at least portions of the first surface of the single layer substrate. The conductive bumps are at least partially exposed in the encapsulant.

Semiconductor device having single layer substrate and method

Growing community of inventors

Seoul, South Korea

Tae Ki Kim