Samsung Electronics Co., Ltd.

Tae-Jong Han

Seung-Heon Lee

Munjun Kim

Kyung-Tae Jang

Daewoong Kim

Jaekang Koh

Junkyu Yang

HongSuk Kim

Sang-Hoon Lee

Myoung-Bum Lee

Won-Seok Jung

Jongmyeong Lee

Jiwoon Im

Seung-Mok Shin

Ju-Wan Kim

Kwangchul Park

Jongwan Choi

Koong-Hyun Nam

Ji-Youn Seo

Byungho Chun

Ji-Woon Im

Ohchel Kwon

Su Jong Kim

Jiyoun Seo

Hyun-Yong Go

Bongcheol Kim

Provided are a method of manufacturing a semiconductor device using a thermally decomposable layer, a semiconductor manufacturing apparatus, and the semiconductor device. The method includes forming an etch target layer on a substrate, forming thermally decomposable patterns spaced apart from each other on the etch target layer, forming a first mask pattern covering at least sidewalls of the thermally decomposable patterns, and removing the thermally decomposable patterns by a heating method to expose a sidewall of the first mask pattern.

Method of manufacturing a semiconductor device using a thermally decomposable layer, a semiconductor manufacturing apparatus, and the semiconductor device

A three-dimensional semiconductor memory device is disclosed. The device may include a substrate including a cell array region and a connection region provided at an end portion of the cell array region, an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes sequentially stacked on the substrate, an upper insulating layer provided on the electrode structure, a first horizontal insulating layer provided in the upper insulating layer and extending along the electrodes, and first contact plugs provided on the connection region to penetrate the upper insulating layer and the first horizontal insulating layer. The first horizontal insulating layer may include a material having a better etch-resistive property than the upper insulating layer.

Three-dimensional semiconductor memory device

A method for fabricating a semiconductor device includes forming a stacked structure on a substrate, forming a first interlayer dielectric covering the stacked structure, and forming a second interlayer dielectric covering the first interlayer dielectric. The stacked structure includes a stepwise shape. The first interlayer dielectric includes at least one step portion having a slope surface connecting a first top surface to a second top surface. The first top surface and the sloped surface define a first angle that is an obtuse angle. A level of the second top surface is higher than a level of the first top surface.

Method for fabricating semiconductor device including a first ILD with sloped surface on a stacked structure and a second ILD on the first ILD

In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.

Vertical memory devices and methods of manufacturing the same

Provided are semiconductor devices and methods of forming the same. A device isolation structure in the semiconductor device includes a gap region. A dielectric constant of a vacuum or an air in the gap region is smaller than a dielectric constant of an oxide layer and, as a result coupling and attendant interference between adjacent cells may be reduced.

Semiconductor devices including device isolation structures and method of forming the same

Methods of forming vertical nonvolatile memory devices utilize carbon-blocking sacrificial capping layers to increase device yield by reducing the likelihood that one or more vertically-stacked layers of materials will lift-off during fabrication. These capping layers may be provided to cover carbon-containing sacrificial layers that are highly polymerized.

Methods of forming semiconductor memory devices having vertically stacked memory cells therein

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Seoul, South Korea

Tae-Jong Han