Samsung Electronics Co., Ltd.

Sk Innovation Co., Ltd.

Fci, Inc.

Sk Corporation

Sabic Sk Nexlene Company Pte. Ltd.

Tae-jin Kim

Hyun-Soon Jang

Ho-cheol Lee

Yun-Ho Choi

Si-Yeol Lee

Churoo Park

Myung-Ho Kim

Chull-Soo Kim

Seung-Hun Lee

Seung-hun Lee

Myung-Ahn Ok

Jong-Sok Hahn

Sang-Ook Kang

Jin-Ho Kim

Tae-Sung Kim

Kyu-Chan Lee

Yong-Woo Kim

Jong-shin Shin

Seung-wook Lee

Jae-youl Lee

Ho-Seong Lee

Dong-cheol Shin

Ju-hwan Yi

Sung Kun Kim

Jang Jin Nam

Jeong-su Jason Lim

Sung-bo Ko

Mal-Ou Lee

Jin-Ho Shin

Byoung-Soo Kim

Tae-Woo Woo

Woon-taek Oh

A transceiver comprises a transmitter that converts a plurality of data components into serial data in response to a first clock signal and transmits the serial data, and a receiver that receives the serial data and converts the serial data into the plurality of data components in response to a second clock signal generated from the serial data. The transmitter adds at least one dummy bit to the serial data at predetermined intervals. The at least one dummy bit includes information regarding a data type of the plurality of data components.

Transceiver having embedded clock interface and method of operating transceiver

The present invention relates to a transition metal complex useful as a transition metal catalyst in the preparation of an ethylene homopolymer or a copolymer of ethylene and an &#x3b1;-olefin, a catalyst composition comprising the same and a process of preparing an ethylene homopolymer or a copolymer of ethylene and an &#x3b1;-olefin using the same. More particularly, it relates to a transition metal complex having a cyclopentadiene derivative and at least one phenyl oxide ligand substituted at the 2-position of phenyl with, for example, a silyl group having a C-Chydrocarbon group or a C-Chydrocarbon group, around a group IV transition metal, with no crosslinkage between the ligands, a catalyst composition comprising the transition metal complex and a cocatalyst selected from the group consisting of an aluminoxane and a boron compound, and a process for preparing an ethylene homopolymer or a copolymer of ethylene and an &#x3b1;-olefin using the same.

Transition metal complexes, catalysts composition containing the same, and process for preparing ethylene homopolymers or copolymers of ethylene and alpha-olefins using the same

A deskew system includes a first voltage control delay receiving a data signal and generating N-numbered delayed data signals obtained by delaying a phase of the data signal in units of 90/N, where N is a natural number that is not less than 1. In response to a phase control signal, a second voltage control delay receives a clock and generates N-numbered delayed clocks by delaying a phase of the clock in units of 90/N. A skew compensation control unit generates a plurality of skew control signals to compensate for skew between the data signal and the clock based on the data signal, the N-numbered delayed data signals, the clock, and the N-numbered delayed clocks.

Deskew system for eliminating skew between data signals and clock and circuits for the deskew system

Disclosed is an arylphenoxy catalyst system for producing an ethylene homopolymer or copolymers of ethylene and &#x3b1;-olefins, and a method of producing an ethylene homopolymer or copolymers of ethylene and &#x3b1;-olefins having a high molecular weight under a high temperature solution polymerization condition using the same. The catalyst system includes a group 4 arylphenoxy-based transition metal catalyst and an aluminoxane cocatalyst or a boron compound cocatalyst. In the transition metal catalyst, a cyclopentadienyl derivative and arylphenoxide as fixed ligands are located around the group 4 transition metal, arylphenoxide is substituted with at least one aryl derivative and is located at the ortho position thereof, and the ligands are not crosslinked to each other. The catalyst includes non-toxic raw materials, synthesis of the catalyst is economical, and thermal stability of the catalyst is excellent. It is useful for producing an ethylene homopolymer or copolymers of ethylene and &#x3b1;-olefins having various physical properties in commercial polymerization processes.

Arylphenoxy catalyst system for producing ethylene homopolymer or copolymers of ethylene and &#x3b1;-olefins

The prevent invention relates to a display apparatus having a display main body adapted to display a picture, a base part adapted to be mounted on an installation surface and supporting the display main body, and a stand part disposed between the base part and the display main body. A first hinge part is disposed between the display main body and the stand part to fold the stand part onto a rear of the display main body. A second hinge part is disposed between the stand part and the base part to rotate the base part between a supporting position where the base part is mounted in a substantially transverse direction with respect to the display main body and a folding position where the base part is mounted substantially parallel to a first end of the stand part. A locking assembly prevents and allows the base part from being and to be rotated between the supporting position and the folding position.

Display apparatus

A bias circuit for a smart power amplifier includes a high power mode bias circuit and a low power mode bias circuit, and operates only one of the bias circuits selectively using a switching circuit according to an input signal. Therefore, the bias circuit of high power mode and the bias circuit of the low power mode are divided and can be optimized according to characteristics of the power. Accordingly, a gain difference with respect to each power can be minimized and the low power mode can be controlled with a small amount of current in a state of initial current with a low power and in a middle power, such that an efficiency of the power amplifier can be improved at low power.

Bias circuit for smart power amplifier

A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Multi-bank dynamic random access memory devices having all bank precharge capability

A semiconductor memory device for a package-state voltage test has a plurality of bonding pads that are electrically connected to an external device in a package state, at least one internal DC voltage generator, at least one switch connected between one of the bonding pads and the internal DC voltage generator. The switch is on during a test mode and is off during a normal mode. The switch controller is connected between at least two of the plurality of bonding pads and serves to control the switch in response to an external switching signal in the test mode. Because of this design, a number of DC voltage tests can be performed without increasing chip size since a general control pad also serves as a DC voltage test pad.

Semiconductor memory device enabling direct current voltage test in package status

Circuit in a semiconductor memory for programming operation modes of the

Synchronous dram having a plurality of latency modes

System for selecting one of a plurality of memory banks for use in an

Semiconductor memory having a plurality of I/O buses

In a semiconductor memory device having a normal memory cell array which includes repeating arrangements of a predetermined data arrangement and whose data is input and output in response to a column select line signal, an arrangement of a redundant cell array is disclosed. The arrangement has the same data arrangement as the minimally repeated unit of said normal memory cell array, wherein the data is in the redundant cell array input and output in response to a redundant column select line signal. According to the arrangement of the redundant cell array, the reliability and yield of the semiconductor memory device are enhanced.

Arrangement of redundant cell array for semiconductor memory device

A semiconductor memory device having a substrate voltage production circuit comprises a time delay circuit. The time delay circuit of the present invention has a simple construction and is provided to facilitate removal of an unwanted substrate current I.sub.SUB existing during a precharge cycle of memory operation. The substrate voltage production circuit requires no additional regulating signals for operation. Latch-up conditions commonly caused by such unwanted substrate currents are eliminated and stable semiconductor memory device operation is achieved.

Semiconductor memory with substrate voltage generating circuit for

Growing community of inventors

Seoul, South Korea

Tae-jin Kim