Skhynix Inc.

Hynix Semiconductor Inc.

Snur & Db Foundation

Tae Jin Kang

Sang Kwon Lee

Young Suk Seo

Ho Uk Song

Jun Hyun Chun

Kyoung Hwan Kwon

Kee Teok Park

Seung Hun Ryu

Woon Bok Lee

Byung Duck Kim

Young Seung Chi

Jung Sim Roh

A semiconductor apparatus includes a clock buffer and a reference voltage generation unit. The clock buffer generates an internal clock signal, based on first and second clock signals, in a first operation mode, and generates the internal clock signal, based on the first clock signal and a reference voltage, when a normal operation test is performed in a second operation mode. The reference voltage generation unit generates the reference voltage when the normal operation test is performed in the second operation mode.

Built-in test circuit of semiconductor apparatus

A semiconductor apparatus includes first and second address buffer groups. The first address buffer group receives first address signals from an external source and outputs the first address signals to a first internal circuit, in first and second operation modes. The second address buffer group receives second address signals from the external source and outputs the second address signals to the first internal circuit, in the first operation mode, and receives third address signals which are generated in a second internal circuit and outputs the third address signals to the first internal circuit, in the second operation mode.

A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.

Semiconductor apparatus

A semiconductor device includes a section signal generator and a decoder. The section signal generator generates a section signal by retarding a pre-section signal including a pulse created during a read operation or a write operation by a delay time that is set according to a level combination of first and second test mode signals. The decoder decodes address signals in response to a pulse of the section signal to generate column selection signals, one of which is selectively enabled, to store an external data in a memory cell of an internal circuit or to output a data stored in a memory cell of an internal circuit.

Semiconductor devices

A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. The final clock generation unit is configured to generate a level signal by latching the shifting signal in synchronization with the sampling clock and generate a final clock from the level signal in response to a burst signal. The write latch signal generation unit is configured to generate an enable signal by latching the final clock and generate a write latch signal for latching and outputting aligned data in response to the enable signal.

Data input circuit

A data output circuit includes a control signal generation block configured to generate a first transfer control signal which is produced in a first read operation and a second transfer control signal which is produced in a second read operation, where the first transfer control signal and the second transfer control signal are generated upon entry into a test mode; and an enable signal generation unit configured to generate first and second enable signals for generating first and second internal clocks, in response to the first and second transfer control signals.

Data output circuit

Semiconductor modules are provided. The semiconductor module includes semiconductor chips with one or more ranks. The semiconductor module includes a mode register configured for storing a first information signal whose logic level is set or determined according to a number of the ranks and an on-die termination (ODT) controller configured for generating an internal control signal for activating an ODT circuit in response to the first information signal. The internal control signal is enabled during a read operation or disabled during a write operation.

Semiconductor modules

A data alignment circuit includes: a select transmission unit configured to selectively transmit a first pulse or ground voltage as a first control pulse and selectively transmit a second pulse or ground voltage as a second control pulse, in response to a control signal; and a data latch unit configured to latch data in response to the first and second pulses and the first and second control pulses, and generate first to fourth data.

Data alignment circuit

A semiconductor system includes a semiconductor memory device configured to, during a test mode, store received data in a memory cell in response to a write command, read the stored data as information data in response to a read command, and internally store the information data, in response to the read command, in synchronization with a pulse generated when a level of the information data changes.

Semiconductor memory device and semiconductor system

A semiconductor integrated circuit includes a first output driver configured to drive a first comparison signal, which is generated by comparing a voltage of a pad coupled to an external resistor with an upper-limit reference voltage, according to drivability determined by a pull-up code and a pull-down code, and output the driven signal as first output data; and a second output driver configured to drive a second comparison signal, which is generated by comparing the voltage of the pad with a lower-limit reference voltage, according to the drivability determined by the pull-up code and the pull-down code, and output the driven signal as second output data.

Semiconductor integrated circuit

Semiconductor modules are provided. The semiconductor module includes a first semiconductor chip configured for storing an information signal that is set in response to a command/address signal and which determines reception of an on-die termination (ODT) signal in a power down mode in response to the information signal to control activation of a first ODT circuit; and a second semiconductor chip configured for sharing and utilizing the first ODT circuit included in the first semiconductor chip.

Control signal generation circuits, semiconductor modules, and semiconductor systems including the same

The present invention relates to an electrically conductive metal composite embroidery yarn and embroidered circuit using thereof which may be applicable to smart textiles. More particularly, this invention relates to an electrically conductive metal composite embroidery yarn and embroidered circuit for smart textiles which can be used as power supply and signal transmission lines. The present invention provides an embroidered circuit which consists of a metal composite embroidery yarn and a dielectric fabric substrate, wherein the electrically conductive metal composite embroidery yarn is embroidered on the dielectric fabric substrate to form a circuit.

Electrically conductive metal composite embroidery yarn and embroidered circuit using thereof

A clock control circuit is presented for reducing unnecessary current consumption. The clock control circuit includes a write enable signal generation unit and a clock enable signal generation unit. The write enable signal generation unit is configured to generate a first write enable signal, which is enabled during a predetermined time period after a write command is inputted, in response to first and second burst signals and a write signal including a pulse generated in response to the write command. The clock enable signal generation unit is configured to generate a clock enable signal, which is enabled during a write operation period, in response to the first write signal and the first write enable signal.

Growing community of inventors

Suwon-si, South Korea

Tae Jin Kang