Hynix Semiconductor Inc.

Skhynix Inc.

Hynic Semiconductor Inc.

Tae-Jin Hwang

Yong-Ju Kim

Ic-Su Oh

Hyung-Soo Kim

Hee-Woong Song

Hae-Rang Choi

Ji-Wang Lee

Jae-Min Jang

Chang-Kun Park

Sung-Woo Han

Kun-Woo Park

Jong-Woon Kim

Joon-Woon Kim

A buffer circuit includes a buffering unit suitable for buffering an input signal and outputting an output signal and a feedback control unit suitable for adjusting a slew rate of the input signal in response to the output signal.

Buffer circuit

A receiver circuit includes a first differential amplification unit including a variable load section, and configured to receive first and second input signals, and to generate first and second output signals, which are amplified based on an impedance value of the variable load section and a voltage difference between the first and second input signals, a second differential amplification unit configured to receive the first and second output signals and to generate a third output signal based on a voltage difference between the first and second output signals, and a signal generating unit configured to generate an equalization signal for controlling the variable load section based on the third output signal.

Receiver circuit with de-emphasis function

A signal amplification circuit includes a differential amplifier configured to receive a first signal and a second signal and generate an output signal, a differential amplifier configured to receive first and second signals and generate an output signal; and a controller configured to control an amount of current flowing in the differential amplifier using the output signal.

Signal amplification circuit

The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

Input buffer circuit of semiconductor apparatus

An interface apparatus for a semiconductor integrated circuit and an interfacing method thereof controls the VOX of differential signals to a target level in response to the differential signals being outputted by an output block. The interface apparatus for a semiconductor integrated circuit includes an output block configured to output differential signals output by an internal circuit a detector configured to detect a timing error of the differential signals; and a controller configured to control a timing of the differential signals output by the internal circuit according to a detection result of the detector.

Interface apparatus for semiconductor integrated circuit and interfacing method thereof

A semiconductor IC device capable of power-sharing includes a first power line configured to be supplied with a first power, a second power line configured to be supplied with a second power, a switching block configured to connect the first power line with the second power line in response to a first control signal, and a power-sharing control block configured to generate the control signal in accordance with a plurality of operation command signals.

Semiconductor IC device having power-sharing and method of power-sharing thereof

A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.

Low power variable delay circuit

A semiconductor integrated circuit equipped with an equalizer which has a circuit structure simpler than that of a related equalizer according to an FFE scheme or a DFE scheme and is capable of preventing a noise component from being amplified. The data receiver includes a plurality of receiver units, wherein each receiver unit includes a plurality of level detectors which detect different levels, and an encoder, in which the level detectors receive data according to a clock signal having a predetermined phase difference and perform an amplification operation including an equalization function based on feedback data, thereby outputting an amplification signal, and wherein level detectors of one receiver unit receive an amplification signal, as the feedback data, from level detectors of another receiver unit that receives a first clock signal having a phase more advanced than a phase of a second clock signal received in one receiver unit.

Data receiver of semiconductor integrated circuit

An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.

Internal supply voltage generating circuit and method for generating internal supply voltage

A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information representing a delay value for delaying the input signal based on a latency value of the input signal and the path information, and a delayer configured to delay the input signal by a delay corresponding to the delay information.

Latency control circuit, semiconductor memory device including the same, and method for controlling latency

A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.

Semiconductor memory device and method for generating output enable signal

A data relay apparatus according to one embodiment described herein can include a phase detection unit that can detect a phase difference between a clock output from a transmitter and a clock output from a receiver, and generate a plurality of phase detection signals, a data relay control unit that can distinguish a difference in clock timing between the clocks of the transmitter and the receiver in response to the plurality of phase detection signals, and output a relay data selection signal and a relay control clock, and a data relay unit that can transmit data output from the receiver to the transmitter in response to the relay data selection signal and the relay control clock.

Data relay apparatus and semiconductor integrated circuit having the same

A semiconductor device includes transmission lines for conveying signals and transition detectors, each of which checks whether a transmission signal on each of the plurality of transmission lines is transited. If the signal is transited, its transition shape is detected. A signal mode determining unit determines signal transmission modes between adjacent transmission lines in response to output signals from the plurality of transition detectors. Delay units are coupled to the respective transmission lines for adjusting transmission delays of the transmission signals depending on corresponding output signal from the signal mode determining units.

Semiconductor device

A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal, and an output unit configured to combine the first and second output signals and output a sampling data signal.

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Gyeonggi-do, South Korea

Tae-Jin Hwang