Lg Electronics Inc.

Tae Il Chung

Eung Tae Kim

A video encoding method, a video encoder, and a Personal Video Recorder (PVR) are disclosed. The PVR includes: a first video decoder for decoding an input MPEG-2 video signal, calculating reference picture information of the MPEG-2 video signal and a motion vector of a reference picture, and outputting the calculated result; a first video encoder for encoding the decoded MPEG-2 video signal into a H.264 video signal using the motion vector and the reference picture information generated from the first video decoder; and a storage unit for storing the H.264 video signal generated from the first video encoder. Therefore, the PVR can effectively transcode the MPEG-2 format image into the H.264 format image, can display a desired image or video signal without deterioration of an image quality, and can quickly transform a compression format of the image into another format.

Video encoding method, video encoder, and personal video recorder

A video decoding system is provided. When a DDR SDRAM is used as an external memory, MBs are rearranged and then stored to minimize memory access operations for the MBs at the DDR SDRAM and unnecessary additional word read operations caused by a DDR characteristic. Accordingly, the video decoding system can efficiently perform a memory access operation on MBs for video display and frame decoding by the video decoder. Specifically, the decoding system can reduce the total video decoding time, thereby allowing a surplus memory use time for additional functions of a digital broadcasting receiver.

Video decoding system with external memory rearranging on a field or frames basis

The present invention provides a video buffer control apparatus for dual video decoding and digital broadcasting receiver. In the present invention, one read block controls the reading of at least two video buffers in performing video decoding on at least two channels, whereby the video buffers can be efficiently controlled and whereby the hardware size of the video buffer control apparatus can be reduced. Moreover, the present invention can simultaneously decode both of the digital broadcasting and a video clip or MPEG still picture having a data format inputted via path different from that of the digital broadcasting.

Video buffer control apparatus for dual video decoding and digital broadcasting receiver thereof

A memory reducing device in an apparatus for receiving moving pictures is applied to the fields such as a digital television receiver, a digital video conference system and the like. The memory reducing device enables to reduce an external memory of an MPEG-2 video decoding chip and obtain standard deviations by predicting the current pixel using a pixel located at the highly-related direction which is determined by having the deviation estimating part measure the relation between the horizontal or vertical direction of the pixels adjacent there between and to be currently encoded. Moreover, the memory reducing device enables to increase a compression ratio as well as provide clear distinction of high definition by reducing the difference less than the bit precision of the current pixel by means of predicting the current pixel by selecting the pixel located at the highly-related direction with the above same method and performing quantization with the prediction.

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Seoul, South Korea

Tae Il Chung