Innochips Technology Co., Ltd.

Moda-innochips Co., Ltd.

Dit Co., Ltd.

Innochips Technologies Co., Ltd.

Tae Hyung Noh

In Kil Park

Gyeong Tae Kim

Myung Ho Lee

Jun Ho Jung

Seung Hun Cho

Ki Joung Nam

Jung Gyu Lee

Young Sul Kim

Song Yeon Lee

Sung Il Park

Tae Geun Seo

Min Soo Lee

Soon Dong Choi

Ki Bum Kwon

Dae Kyum Kim

Jung Hun Lee

In Seob Jung

Sung Cheol Park

Hyun Chul Jung

Seong Bae Park

Seung Hwan Lee

Wan Park

Gyeong-Tae Kim

Euy Ho Shin

Byung Yul Choi

Hyun Mo Kang

Seong Cheol Park

Jin Hwan Kim

Hee Seob Shin

Ki Beom Kwon

The present disclosure relates to a multilayer ceramic substrate preparation method. The multilayer ceramic substrate preparation method according to the present disclosure includes firing a plurality of ceramic green sheets, to create a plurality of ceramic thin films; forming a via hall in each of the plurality of ceramic thin films; filling the via hall of the plurality of ceramic thin films with conductive paste, and heat treating the via hall filled with the conductive paste, to form a via electrode; printing a pattern on a cross section of each of the plurality of ceramic thin films, and heat treating the printed pattern, to form an inner electrode; applying a bonding agent on the cross section of each of the ceramic thin films excluding an uppermost ceramic thin film of the plurality of ceramic thin films; aligning and laminating each of the plurality of ceramic thin films such that each of the plurality of ceramic thin films is electrically connected through the via electrode and the inner electrode; and firing or heat treating the laminated plurality of ceramic thin films.

Multilayered ceramic substrate and method for manufacturing same

In accordance with an exemplary embodiment, a power inductor includes a body, a base disposed in the body, and a coil pattern disposed on at least one surface of the base, in which the body includes metal powder, a polymer, and a thermal conductive filler and the base is formed by bonding a copper foil to both surfaces of a metal plate comprising iron.

Power inductor

The present disclosure provides a power inductor, which includes a body, at least one substrate provided inside the body, at least one coil pattern provided on at least one surface of the substrate, and an insulation layer formed between the coil pattern and the body, wherein the insulation layer is formed of parylene.

The present invention suggests a power inductor comprising: a body; at least one substrate provided on the inside of the body; at least one coil pattern provided on at least one surface of the substrate; and an insulating layer formed between the coil pattern and the body, wherein at least a part of the substrate is removed and the body is filled in a region where the substrate is removed.

Provided is a laminated chip device including a first laminate in which a plurality of conductor patterns formed on a plurality of sheets are connected to each other through a via formed to penetrate at least a sheet, and a second laminate provided over or below the first laminate and having a plurality of internal electrode patterns formed on a plurality of sheets, and the internal electrode patterns have a non-conductive region in at least a portion of an area corresponding to the via.

Laminated chip device

The present disclosure includes: a laminate in which a plurality of sheets are laminated; two or more noise filters provided spaced apart by a predetermined distance from each other in the laminate and respectively provided with a plurality of coil patterns; an external electrode provided outside the laminate and connected to the two or more noise filters; and a connection electrode provided outside the laminate being spaced apart from the external electrode to connect the two or more coil patterns.

Circuit protection device having noise filters

Provided is a piezoelectric vibrating device including a case provided with a certain space therein, a piezoelectric vibrating member provided in the case and vibrating according to an applied voltage, a weight member provided in the case and connected to a part of the piezoelectric vibrating member in a vibration direction of the piezoelectric vibrating member, and a limitation member for limiting movement of the weight member.

Piezoelectric vibrating device

Disclosed is a portable piezoelectric speaker including a body configured to be coupled to and separated from a rear surface of an electronic device, and a piezoelectric speaker module coupled to a predetermined area of the body, wherein the piezoelectric speaker module includes a piezoelectric device, and a vibration transfer member provided to be in contact with at least one area of the piezoelectric device and to be spaced apart from at least one surface of the piezoelectric device.

Portable piezoelectric speaker and electronic device having the same

Provided are a complex device including a piezoelectric device, a wire patch cell (WPC) antenna disposed on one surface of the piezoelectric device, the WPC antenna being connected to two antenna patterns that are vertically spaced apart from each other, and a near field communication (NFC) antenna disposed outside the WPC antenna and an electronic device having the same.

Complex device and electronic device having the same

Provided is a circuit protection device including a plurality of sheets selectively formed with at least one coil pattern, at least one withdrawal electrode, at least one hole filled with a conductive material, and at least one capacitor electrode and at least two inductors and at least two capacitors, in which the at least one coil pattern forms one inductor and a capacitor is formed between the capacitor electrode and the coil pattern.

Circuit protection device

The present disclosure relates to a stacked chip device including a first stack unit comprising a plurality of electrode patterns respectively disposed for a unit device region and common electrode patterns formed to be connected to cross the unit device regions, a second stack unit disposed on a top portion of the first stack unit and comprising a plurality of first conductor patterns, and a third stack unit disposed on a bottom portion of the first stack unit and comprising a plurality of second conductor patterns, wherein the first and second conductor patterns are formed on a plurality of sheets, the first and second conductor patterns formed on one sheet are formed across a plurality of unit device regions, and the first and second conductor patterns are connected vertically through vias formed penetrating through at least some of the sheets.

Stacked chip device

Provided is a sensor including an insulating layer, at least two heater patterns separated in one direction in the insulating layer and electrically connected to each other, at least two sensing electrode patterns insulated form the heater patterns, separated in the one direction in the insulating layer, and electrically connected to each other, and a sensing material, at least a part of which is buried in the insulating layer to contact the sensing electrode patterns.

Growing community of inventors

Siheung-si, South Korea

Tae Hyung Noh