Samsung Electronics Co., Ltd.

Tae Hyung Lee

Sang-Kuk Kim

Gwang-Hyun Baek

O Ik Kwon

Yun Seung Kang

Hye Ji Yoon

Su Jin Jeon

A semiconductor memory device in which performance is improved by reducing a wiring resistance is provided. The semiconductor memory device comprising an inter-wiring insulation film on a substrate, a first wiring pattern extending in a first direction, in the inter-wiring insulation film, a barrier insulation film that is on an upper surface of the inter-wiring insulation film, a barrier conductive pattern electrically connected to the first wiring pattern, in the barrier insulation film, a memory cell electrically connected to the barrier conductive pattern and including a selection pattern and a variable resistor pattern, and a second wiring pattern extending in a second direction intersecting the first direction, on the memory cell, wherein a width of the barrier conductive pattern in the second direction is different from a width in the second direction of a portion of the memory cell that is adjacent to the barrier conductive pattern.

Growing community of inventors

Hwaseong-si, South Korea

Tae Hyung Lee