Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Doosan Corporation

Samsung Mobile Display Co., Ltd.

Samsung Sdi Co., Inc.

Tae-hyung Kim

Kyoung-Soo Kim

Sang-Yeop Baeck

Jae-Seung Choi

Dae-young Moon

Jin-Seok Hong

Jeoung-Gwen Lee

Eui-Gyu Kim

Jun-Hee Son

Jung-Hwan Choi

Tae-Soo Kim

Jung-Ho Do

Young-jin Kim

Chan-Ho Lee

Byoung-Seong Jeong

Dong-Wook Seo

Kang-tae Kim

In-Hak Lee

Sang-shin Han

Siddharth Gupta

Jae-hyun Lim

Jin-Woo Park

Jong-Kyu Kim

Se-Ki Park

Sang-Su Kim

Sang-Yeol Kim

Sung-wook Kang

Jung-Sub Lee

Eunjung Lee

Sung-Hwan Kim

Sung-jae Moon

Min-Soo Choi

Jin-Soo Shin

Seung-Wook Chang

Sunghyun Park

Inhak Lee

Hyunsu Choi

Chang-Ju Shin

Se-Ho Lee

Young-Suk Ha

SangShin Han

Kwang-Hyun Ko

Je-Hyun Song

Sung-geun Kim

Sang-Min Kang

Wee-Joon Jeong

Yong-Gwang Won

Iee-Gon Kim

Soung-Kwan Kimn

JaeSeung Choi

Gennady Ivanov

Tae-Hun Lee

Sung-Won Yang

Alexander Larionov

Chang-sik Yun

Yong-Ha Choi

You-Kyung Cho

Jung-Wook Chai

Sang-Do Lee

Ki-Hong Song

An integrated circuit includes a plurality of layers stacked in a first direction, a plurality of unit circuits at least partially overlapping each other in a second direction that is perpendicular to the first direction and configured to operate in parallel with one another, control circuitry configured to generate a control signal to control the plurality of unit circuits, and a multi-layer conducting line configured to transfer the control signal from the control circuitry to the plurality of unit circuits. The multi-layer conducting line may be integrally formed in a wiring layer and a via layer and extends in the second direction. The wiring layer and the via layer may be adjacent to each other.

Integrated circuits including multi-layer conducting lines

Provided is an integrated circuit which includes: a plurality of conductive lines extending in a first horizontal direction on a plane separate from a gate line, and including first and second conductive lines; a source/drain contact having a bottom surface connected to a source/drain region, and including a lower source/drain contact and an upper source/drain contact which are connected to each other in a vertical direction; and a gate contact having a bottom surface connected to the gate line, and extending in the vertical direction, in which the upper source/drain contact is placed below the first conductive line, and the gate contact is placed below the second conductive line. A top surface of the lower source/drain contact may be larger than a bottom surface of the upper source/drain contact.

Integrated circuit having heterogeneous gate contacts over active regions

A system on chip includes a clock generator configured to generate a clock signal, and output the clock signal to a component device external to the system on chip. The system on chip further includes a duty ratio determiner configured to determine a component duty ratio, in response to a response that is received from the component device according to the clock signal, and a duty ratio adjustor configured to adjust a current duty ratio of the clock signal to the component duty ratio, and output the clock signal of which the current duty ratio is adjusted, to the component device.

System on chip performing clock training and computing system including the same

A method of displaying for allowing a plurality of application windows to be easily controlled and a display device therefor are provided. A method of displaying a screen on a display device includes displaying a button on a touch screen; splitting the touch screen into a plurality of regions based on the position at which the button is displayed, receiving a touch input to move a displayed button, obtaining a slope value of a line connecting a start point of the touch input to an end point thereof, selecting a region corresponding to the slope value from among the plurality of regions split, and moving the button to a certain position included in a selected region.

Display device and method of displaying screen on said display device

A memory device includes a first write assist circuit providing a cell voltage or a write assist voltage to a first memory cell connected with a first bit line pair, a first write driver that provides write data to the first memory cell through the first bit line pair, a second write assist circuit that provides the cell voltage or the write assist voltage to a second memory cell connected with a second bit line pair, and a second write driver that provides write data to the second memory cell through the second bit line pair. One of the first and second write assist circuits provides the write assist voltage in response to a column selection signal for selecting one write driver, which provides write data, from among the first, and second write drivers, and the other thereof provides the cell voltage in response to the column selection signal.

Memory devices comprising a write assist circuit

Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

Voltage control circuit including assist circuit and memory device including the same

Integrated circuit having heterogeneous source/drain and gate contacts

A multi-functional apparatus for testing and etching a substrate capable of increasing spatial efficiency and manufacturing efficiency by performing testing and etching operations in a same chamber body and a substrate processing apparatus including the same, the multi-functional apparatus including a chamber body having an entrance into which the substrate is injected in one of its sides and an exit from which the substrate is ejected in another one of its sides; a transfer unit disposed inside of the chamber body and for transferring the injected substrate in a direction from the entrance to the exit; a laser etching unit disposed on an upper portion of the transfer unit and for etching a part of the substrate disposed on the transfer unit; and a testing unit for testing the substrate disposed on the transfer unit.

Multi-functional apparatus for testing and etching substrate and substrate processing apparatus including the same

A method of managing a memory of a device is provided. The method includes acquiring amount of memory use information of the device, estimating a memory use pattern, based on the amount of memory use information of the device, and acquiring an amount of memory of the device, based on the estimated memory use pattern.

Method and apparatus for securing sufficient memory in a device

A method and an electronic device for providing a screen mirroring service are provided. The method includes connecting a control channel to at least one other electronic device when an electronic device executes a screen mirroring service, transmitting screen data comprising an added virtual key, to the other electronic device, and performing a function based on a control signal corresponding to using the virtual key received from the other electronic device over the control channel.

Method and apparatus for providing of screen mirroring service

An organic light emitting display apparatus and a method of manufacturing the same are disclosed. The organic light emitting display apparatus includes, for example, a bus electrode, an insulating layer covering the bus electrode and having a bus electrode hole exposing at least a part of the bus electrode, a pixel electrode formed on the insulating layer and electrically coupled with the bus electrode, a pixel defining layer exposing a part of the pixel electrode and a part of the bus electrode, a first intermediate layer on the pixel defining layer and the pixel electrode, the first intermediate layer having a first opening to expose the part of the bus electrode, an emission layer disposed on the first intermediate layer, and an opposite electrode to correspond to the pixel electrode and the bus electrode and contacting the bus electrode through the first opening and the bus electrode hole.

Organic light emitting display apparatus and method of manufacturing the same

A system for controlling a video is provided. The system includes a terminal which transmits a flush command to an external device to delete buffered data in a buffer of the external device when a search command for moving to a location of specific data of a video is generated while data of the video is streamed to the external device and which then transmits to the external device the specific data located in relation to the search command, and an external device which deletes the buffered data in the buffer when the flush command is received from the terminal while a video streamed from the terminal is reproduced and which buffers the specific data of the video received from the terminal in the buffer to be output.

Apparatus and method for controlling a video

Growing community of inventors

Yongin-si, South Korea

Tae-hyung Kim