Qualcomm Incorporated

Tae Hyun Kim

Jung Pill Kim

Seung Hyuk Kang

Kangho Lee

Hari Rao

Xia Li

Xiaochun Zhu

Jungwon Suh

Wuyang Hao

Matthew Michael Nowak

Wah Nam Hsu

Asaf Ashkenazi

Steven Mark Millendorf

Nicholas K Yu

Wenqing Wu

Jung Pil Kim

Hari M Rao

Steven M Millendorf

A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ.

Non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction

A system and method to select a reference cell is disclosed. In a particular embodiment, a method is disclosed that includes receiving an address corresponding to a bit cell within a first bank of a memory. The method also includes accessing a second reference cell of a second bank of the memory in response to a first reference cell in the first bank being indicated as bypassed.

System and method to select a reference cell

A resistance-based memory has a two-diode access device. In a particular embodiment, a method includes biasing a bit line and a sense line to generate a current through a resistance-based memory element via a first diode or a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.

Resistance based memory having two-diode access device

A Magnetic Random Access Memory (MRAM) logic circuit includes read sensing circuitry having a first level corresponding to a first category of logic circuitry and a second logic level corresponding to a second category of logic circuitry. The logic circuitry may be switchable between circuitry having the first logic level and circuitry having the second logic level according to the category of the logic circuit being implemented.

Programmable logic sensing in magnetic random access memory

Resistance memory cells of MRAM arrays are designated as reference cells and programmed to binary 0 and binary 1 states, reference cells from one MRAM array at binary 0 and at binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of another MRAM array, reference cells from the other MRAM array at binary 0 and binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of the one MRAM array.

System and method for shared sensing MRAM

Magnetic tunnel junctions (MTJs) in magnetic random access memory (MRAM) are subject to read disturb events when the current passing through the MTJ causes a spontaneous switching of the MTJ due to spin transfer torque (STT) from a parallel state to an anti-parallel state or from an anti-parallel state to a parallel state. Because the state of the MTJ corresponds to stored data, a read disturb event may cause data loss in MRAM devices. Read disturb events may be reduced by controlling the direction of current flow through the MTJ. For example, the current direction through a reference MTJ may be selected based on the state of the reference MTJ. In another example, the current direction through a data or reference MTJ may be alternated such that the MTJ is only subject to read disturb events during approximately half the read operations on the MTJ.

Magnetic random access memory (MRAM) read with reduced disturb failure

A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.

Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction

A Magnetic Random Access Memory (MRAM) includes read sensing circuitry having an equalizer device configured between a bit cell output node and a reference node of the bit cell. The equalizer is turned on to couple the output node to the reference node during an initial portion of a read operation and to decouple the output node from the reference node after an equalization delay period. A sense amplifier is enabled to provide a data output from the bit cell only after the delay period and decoupling of the output node from the reference node to provide balanced sensing speed of data represented by parallel and antiparallel state magnetic tunnel junctions (MTJs).

Read sensing circuit and method with equalization timing

A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied during a write operation.

Row-decoder circuit and method with dual power systems

A large scale memory array includes a uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects.

Magnetic random access memory (MRAM) layout with uniform pattern

Systems and methods of testing a reference cell in a memory array are disclosed. In a particular embodiment, a method of testing a reference cell in a memory array includes coupling a first reference cell of a first reference cell pair of the memory array to a first input of a first sense amplifier of the memory array. The method also includes providing a reference signal to a second input of the first sense amplifier. The reference signal is associated with a second reference cell pair of the memory array.

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San Diego, CA, United States of America

Tae Hyun Kim