Lg Semicon Co., Ltd.

Goldstar Electron Co., Ltd.

Tae-Hyoung Kim

Jin-Hong Ahn

Young-Hyun Jun

Jae-Goo Lee

Chang-Man Khang

Ha-Soo Kim

Sung-Ho Wang

The semiconductor memory according to the present invention employs a plurality of sense amplifier drivers which individually control the sense amplifiers, or control groups of sense amplifiers, in the semiconductor memory. More specifically, the sense amplifier drivers control whether associated sense amplifiers are connected to sense amplifier array input/output lines. In this manner fewer sense amplifiers are connected to the sense amplifier array input/output lines, reducing overall current consumption.

Semiconductor memory device with improved sense amplifier driver

A semiconductor memory device is provided that enhances data output speed. The semiconductor uses dual memory arrays with differing activation voltage levels. The semiconductor memory includes a first memory cell array having multiple memory cells and a second memory cell array having more memory cells than the first memory cell array. First and second row decoders respectively receive first and second row addresses to respectively generate an activation signal for a word line in the first memory cell array and subsequent word lines in the second memory cell array. A column decoder receives and decodes a column address to generate a bit line selection signal for the first and second memory cell arrays. The semiconductor device further includes a sense amplifier, which is coupled to bit lines selected based on the bit line selection signals, that detects a potential difference between the bit lines caused by data and amplifies the potential difference. The sense amplifier also refreshes the data on the memory cell from which the data was read.

Semiconductor device having multiple sized memory arrays

A semiconductor memory device and method are provided that enhance data output speed of a DRAM or the like by reducing the time difference between the data output operation from a preceding word line and the data output operation from a succeeding word line. The semiconductor memory device includes a memory cell array arranged with multiple memory cells having a corresponding word line and a corresponding bit line, a row decoder for decoding a row address to select and activate a word line of the memory cell array and a sense amplifier for sensing and amplifying the data in a memory cell coupled to the activated word line when the data is applied to the corresponding bit line. The semiconductor further includes first and second latches respectively storing data using the sense amplifier taken from a memory cell coupled to a preceding activated word line and a succeeding activated word line. A switching block controls the data path between the sense amplifier and the first latch, or the sense amplifier and the second latch and a column decoder selects and applies the data stored in the first or second latch to a data bus. A data bus sense amplifier amplifies the data applied to the data bus before transmitting it to a data output buffer.

Semiconductor memory device and method

An improved burn-in checking apparatus for a semiconductor memory device in which a latch-type decoder is connected between a row address predecoder for decoding an internal or external address when it is inputted and a word line driving unit for driving a word line unit to latch a high level signal for keeping an enabled condition, so that when a burn-in flag is applied, an output from the row address predecoder is decoded again, and a word line selected according to such decoding is continuously enabled even when a next word line is selected in accordance with decoding of a next row address signal. The apparatus has the advantage that by sequentially enabling all the word lines within almost one minute and latching the enabled condition until the completion of the burn-in checking, the actual time consumed in real checking is little increased, and in addition, the contamination of the device characteristic due to an increase in a momentary current amount can be effectively prevented.

Burn-in checking apparatus for semiconductor memory device

A bit line structure is disclosed. Which includes: sense amplifiers each connected to two pairs of bit lines BL and /BL through bit line selecting switches, to the bit line a plurality of cells are connected, includes: a first bit line pair BL and /BL and a second bit line pair BL and /BL formed by dividing a bit line disposed within a same column respectively in a cell array; a first connecting bit line for connecting the bit line BL of said second bit line pair to said sense amplifier; a second connecting bit line for connecting the bit line /BL of said second bit line pair to said sense amplifier; said second connecting bit line having two crossing sections 25 crossing with another second connecting bit line for connecting a bit line BL of a second bit line belonging to an adjacent sense amplifier; and bit line selecting switches for connecting said first bit line pair and said second bit line pair respectively to said sense amplifier, whereby a number of memory cells connected to each bit line is reduced to 1/2 compared with the conventional technique, the bit lines are arranged 3-dimensionally to eliminate the area loss in carrying out the layout, and particularly, the connecting bit lines are made of a conductive material which has a smaller resistance than a conductive material of the bit lines.

Bit line structure with bit line pass over configuration

Bit line structure

A method for driving bit line selecting signals is disclosed, in which the DRAM cell includes a plurality of memory cell arrays, sense amplifiers, bit lines, bit line equalizer sections, bit line selecting sections, data input/output sections, and bit line selection signal generating sections. According to the present invention, the bit line selecting signals operate in such a manner that: during a bit line selection, a bit line selecting signal for connecting one pair of bit lines among the n pairs of bit lines to the sense amplifier is made to have a voltage level capable of connecting the bit lines to the sense amplifier by the help of the bit line selecting section without a voltage loss; the other bit line selecting signals corresponding to the non-selected remaining bit lines are given a voltage incapable of connecting the bit lines the sense amplifier by the bit line selecting section; thereafter, during the pre-charging for a bit line equalization, the bit line selecting signal corresponding to the bit line which was selected just before is given a voltage capable of connecting the bit lines to the sense amplifier by the help of the bit line selecting section; and the bit line selecting signals which do not correspond to the bit line selected just before are maintained without a voltage shifting.

Growing community of inventors

Kyungki-do, South Korea

Tae-Hyoung Kim