Samsung Electronics Co., Ltd.

Sungkyunkwan University

Tae-Hyoung Kim

Young-Bum Kim

Sung-Jin Park

Seung-Hoon Choi

Kwang-Jin Lee

Jung-Hwan Choi

Tae-Han Bae

Nam-seog Kim

Jin-Young Oh

Jeong-Ho Yeo

Uk-Rae Cho

Young-Woo Kwak

Ji-Suk Kwon

Yong-Jin Yoon

Hyun-jin Cho

Yong-Woo Jung

Young-Ik Eom

Hyun-Su Jang

Zhen Zhao

Youn-woo Kim

Hyun-Woo Choi

Gye-Hyeon Gyeong

Jeong-Suk Yang

Kwang-Sun Ko

The present invention relates to a method of embodying a cooperation system between SEND and IPSec in an IPv6 environment. The cooperation system between SEND and IPSec in accordance with the present invention includes: receiving an authentication completion report message including a first IP address of a host whose authentication is completed by the SEND; generating new authentication information corresponding to the host and storing the new authentication information in a temporary storage area, if authentication information for the host is not present in the temporary storage area, wherein the authentication information includes the first IP address; and if an authentication check request message including a second IP address is received from the IPSec, checking whether the second IP address is present in the temporary storage area, and sending the result of checking to the IPSec. The present invention allows the authentication information shared between SEND and IPSec in a mobile environment, where the network is frequently accessed, enabling IPSec secure communication at a lower cost.

Cooperation method and system between send mechanism and IPSec protocol in IPV6 environment

An impedance control circuit includes an impedance detector, an output driver and an impedance controller. The impedance detector generates a first output value to a detection pad connected between an external determination resistor and a pull-up transistor array, and outputs a second output value to a resistance divider terminal commonly connected between a pull-up and pull-down transistor array in response to a pull-up control code data and a pull-down control code data. The output driver has a commonly connected pull-up and pull-down transistor array, and a compensating unit connected to the pull-up and pull-down transistor array of the output driver, to compensate for quantization error of the pull-up and pull-down control code data. The impedance controller performs a comparison and counting operation so that the first and second output values of the impedance detector become approximated to a predetermined reference value, and generates the pull-up and pull-down control code data.

Impedance control circuit in semiconductor device and impedance control method

Provided is an output impedance circuit, which has a constant output impedance regardless of a pad voltage, and an output buffer circuit including the output impedance circuit. The output impedance circuit includes an output stage and an impedance control stage. The output stage outputs a current corresponding to a DC bias voltage via an output terminal, and the impedance control stage controls the current flowing through the output stage in response to an output signal. The output stage includes a resistance component and a first MOS transistor. A first terminal of the resistance component is connected to the output terminal. A first terminal of the first MOS transistor is connected to a second terminal of the resistance component, a second terminal of the first MOS transistor is connected to a voltage source, and an input signal is input to a gate of the first MOS transistor.

Output impedance circuit and output buffer circuit including the same

A drive circuit having impedance control includes an impedance matching array unit having a plurality of transistors, the plurality of transistors selectively driven in accordance with an array drive control signal generated by control code data, and an update prohibition control unit for generating a transfer control signal to prohibit driving the transistors during a first time interval occurring when internal data transition, and applying the transfer control signal to the impedance matching array unit.

Impedance controllable ouput drive circuit in semiconductor device and impedance control method therefor

An impedance controller includes a current mirror section to generate an impedance current. At least one detector includes a transistor array and an impedance corresponding to the impedance current, the at least one detector operating responsive to a code generator. And an at least one code generator generates a first code to adjust a gate voltage of the transistor array by comparing an output of the at least one detector to a reference voltage and generates a second code to adjust a size of the transistor array by comparing the output from the at least one detector to the reference voltage.

Impedance controller and impedance control method

A semiconductor device includes an output impedance control circuit, connected to a ZQ pad and an output buffer circuit, for controlling an impedance of the output buffer circuit according to an impedance of an external resistor connected with the ZQ pad.

Semiconductor device with impedance control circuit

A synchronous mirror delay circuit comprises a delay monitor circuit for delaying a reference clock signal from a clock buffer circuit. A forward delay array sequentially delays an output clock signal of the delay monitor circuit to generate delay clock signals, and the mirror control circuit detects a delay clock signal synchronized with the reference clock signal among the delay clock signals. A backward delay array delays a clock signal delayed by the mirror control circuit, and a clock driver receives an output clock signal of the backward delay array to generate the internal clock signal. A locking range control circuit controls a delay time of each clock signal transferred to the delay monitor circuit by the amount of a delay time of each signal transferred to the clock driver when none of delay clock signals of the forward delay array is synchronized with the reference clock signal.

Synchronous mirror delay circuit with adjustable locking range

There is provided an integrated circuit which performs data input/output operations through a transmission line with a predetermined impedance. The integrated circuit includes a driver having a plurality of driving units, in which the driving units input/output data from/to the transmission line, and a controller for inputting an output data signal and applying a plurality of control signals to the driver, in which the control signals are generated in response to an output activation signal and impedance code signals related to states of the impedance. At least one driving unit is driven in response to the control signals, and the driver includes an on-chip termination circuit connected to an input buffer.

Integrated circuit with on-chip termination

An output impedance control circuit of a semiconductor device. A first transistor is connected to a pad and a level controller controls a gate voltage of the first transistor in response to a voltage of the pad and a reference voltage. A MOS array is connected between the pad and a power supply voltage and supplies current to the pad in response to an impedance control code. A first control circuit generates the impedance control code in response to whether a voltage of the pad is converging to the reference voltage. A second control circuit controls a pull-up impedance of the output buffer circuit in response to the first impedance control code when a voltage of the pad is converging to the reference voltage.

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Gyeonggi-do, South Korea

Tae-Hyoung Kim