Micron Technology Incorporated

Other

Nan Ya Technology Corporation

Tae Hyoung Kim

Charles L Ingalls

Howard Kirsch

Christopher John Kawamura

Scott James Derner

Yuan He

David L Pinney

Corrado Villa

Si-Woo Lee

Sangmin Hwang

K Shawn Smith

Jeremy J Gum

Greg A Blodgett

Huy Thanh Vo

Shigeki Tomishima

Chulmin Jung

Jiyun Li

Brenton P Van Leeuwen

Byung Sick Moon

Michael V Cordoba

Todd A Merritt

Beau D Barry

Jonathan T Doebler

Sang-Kyun Park

Yu-Wen Huang

Mingshiang Wang

Risa Asmus-Dorweiler

Joanne Elizabeth Birnberg

Daniel H Dunn

Denise Lerolle-Lelorrain

Methods, systems, and devices for sensing a memory with shared sense components are described. A device may activate a word line and a plate line each coupled with a set of memory cells, where each memory cell of the set of memory cells is coupled with a respective digit line of a set of digit lines. The device may activate a set of switching components to couple each digit line of the set of digit lines with a respective sense component of a set of sense components, where each switching component of the set of switching components is coupled with a respective memory cell of the set of memory cells. The device may sense the set of memory cells based on activating the word line and the plate line and based on coupling the set of digit lines with the set of sense components.

Sensing scheme for a memory with shared sense components

A memory device includes a level shifting circuitry. The level shifting circuitry includes an input circuitry configured to receive an input to the level shifting circuitry in a first voltage domain. The level shifting circuitry also includes a cross-junction circuitry electrically coupled to a first node of the input circuitry comprising multiple transistors that are electrically coupled in a cross-junction. The level shifting circuitry also includes an output staging circuitry electrically coupled to a second node of the cross-junction circuitry. The output staging circuitry is configured to transmit an output in a second voltage domain. The output staging circuitry includes a transistor and voltage stress reduction circuitry configured to mitigate degradation of the transistor by reducing voltage stresses across the transistor during transitions in the level shifting circuitry.

Systems and methods for improved reliability in voltage level shifters

A boost circuit is used to provide boosting voltage to a common boost node of a plurality of sub-word line drivers in memory systems and devices. The boost circuit includes a Metal Insulator Metal Capacitor. By using the boost circuit, the plurality of sub-word line drivers are configured to output a certain voltage to local word lines without using high DC generators to generate high voltages (4.2 volts or more). The area of the semiconductor substrate used for fabricating the sub-word line drivers is reduced, and thus reduce the cost or increasing the capacity of the memory devices.

Sub-word line driver having common gate boosted voltage

Apparatuses, systems, and methods for compensated sense amplifier with cross-coupled n-type transistors. A sense amplifier has a pair of p-type transistors coupled between a system voltage and respective first and second gut nodes. When a command signal is active, the p-type transistors are coupled in a diode fashion from the system voltage to the respective gut nodes. The amplifier also has a pair of n-type transistors which are cross coupled, where a first n-type transistor has a node coupled to the first gut node and a gate coupled to the second gut node and the second n-type transistor has a node coupled to the second gut node and a gate coupled to the first gut node. Each of the n-type transistors may have a separate current flowing through them and respective one of a pair of feedback transistors to a ground voltage.

Apparatuses and methods for compensated sense amplifier with cross coupled N-type transistors

Apparatuses, systems, and methods for single-ended sense amplifiers. A memory device may include a number of sense amplifiers used to read the voltage of memory cells along digit lines. Double-ended sense amplifiers are coupled to two digit lines. Single-ended sense amplifiers are coupled to a single digit line. The memory cells of an edge word line of a memory array may alternately be coupled to a single-ended sense amplifier or a double-ended sense amplifier. The use of single-ended sense amplifiers may reduce a footprint for a given number of memory cells in the array.

Apparatuses and methods for single-ended sense amplifiers

A sense amplifier can be formed outside of/horizontally adjacent to an array of vertically stacked tiers of memory cells. Memory cells can be sensed via multiplexors formed under the array that can operate to couple vertical sense lines (to which the memory cells are coupled) to horizontal sense lines (to which the sense amplifier is coupled).

Multiplexors under an array of memory cells

A FX phase driver for a memory device having a first driver circuit including a first pull-up circuit configured to drive a first phase signal to a first high state value and a first pull-down circuit configured to drive the first phase signal to a first low state value. The phase driver also including a second driver circuit including a second pull-up circuit configured to drive a second phase signal to a second high state value that is higher than an active state voltage level of a word line in the memory device and a second pull-down circuit configured to drive the second phase signal to a second low state value. The second pull-down circuit includes a stabilization circuit configured to provide a resistive path for a leakage current in the second pull-down circuit when the second pull-up circuit drives the second phase signal to the second high state value.

FX driver circuit

Methods, systems, and devices for driving word lines using sub word line drivers are described. A memory array may include a plurality of sub-arrays arranged with gaps in between. Word lines may be arranged across multiple sub-arrays and drive access transistors that are used to selectively access rows (e.g., rows of memory cells) within the sub-arrays. In some examples, signals applied to selection devices driving the word lines may be over-driven for a duration at or near the desired transitions of the word line, and some signals may be driven to a relatively high level for a duration around the high and low transitions of a global row line. Whether a signal is over driven or driven to a relatively high level may depend on the type or types of transistors used in each word line driver.

Sub word line driver

Apparatuses and methods including memory cells, digit lines, and sense amplifiers are described. An example apparatus includes a pair of digit lines including first and second digit lines, a sense amplifier coupled to the pair of digit lines and configured to amplify a voltage difference between the first and second digit lines when activated, and a plurality of memory cells. A memory cell of the plurality of memory cells includes a first node coupled to the first digit line and includes a second node coupled to the second digit line. The memory cell of the plurality of memory cells is configured to store a respective voltage and/or charge at a respective cell node and couple the respective voltage and/or charge to the first node when activated.

Apparatuses and methods including memory cells, digit lines, and sense amplifiers

An access line multiplexor can be formed under vertically stacked tiers of memory cells. The multiplexor can include a first transistor coupled to a vertical access line, to a horizontal access line, and to a second transistor. The second transistor can be coupled to a power supply. The transistors can be n-type metal oxide semiconductor transistors.

Vertical access line multiplexor

A memory device includes a level down shifting driver circuit. The level down shifting driver circuit include input circuitry having at least one input port, and a cross-junction circuitry electrically coupled to the input circuitry and configured to receive a first signal from the input circuitry to drive one or more devices included in the cross-junction circuitry. The level down shifting driver circuit further includes an output drive circuitry electrically coupled to the cross-junction circuitry and configured to receive a second signal from the cross-junction circuitry, wherein the output drive circuitry comprises an output line configured to deliver a first voltage output based on a first input voltage received by the input circuitry, and a second voltage output based on a second input voltage received by the input circuitry.

Systems and methods for level down shifting drivers

A memory device can comprise an arrays of memory cells comprising a plurality of vertically stacked tiers of memory cells, a respective plurality of horizontal access lines coupled to each of the plurality of tiers of memory cells, and a plurality of vertical sense lines coupled to each of the plurality of tiers of memory cells. The array of memory cells can further comprise a plurality of multiplexors each coupled to a respective vertical sense line, wherein each of the plurality of multiplexors includes a first portion and a second portion, the first portion is coupled to the array of memory cells and the second portion is formed on a substrate material. The array of memory cells can further comprise a semiconductor under the array (SuA) circuitry comprising a plurality of sense amplifiers, each sense amplifier coupled to a respective subset of the plurality of multiplexors.

Growing community of inventors

Boise, ID, United States of America

Tae Hyoung Kim