Samsung Electronics Co., Ltd.

Tae-Hong Kwon

Yoonjae Lee

Kiwhan Song

Gyosoo Choo

Seokin Hong

Yeji Shin

Disclosed is a charge pump of a flash memory, which includes a first stage pump that is connected between an output terminal and a first pump node, and a second stage pump that is connected between the first pump node and a second pump node. The first stage pump includes a first switch circuit that is connected between a power terminal and the first pump node and provides a power supply voltage to the first pump node in response to a first stage signal, in a normal operation, and a first pump circuit that generates a first pumping voltage by using a voltage of the first pump node in response to a first clock signal and provides the first pumping voltage to the output terminal. The first switch circuit blocks a current flow from the first pump node to the power terminal in a sudden power-off event.

Charge pump having switch circuits for blocking leakage current during sudden power-off, and flash memory including the same

Various example embodiments provide a flash memory device, comprising a cell string; a page buffer connected to the cell string and a bit line and configured to sense data stored in a selected memory cell by precharging a sensing node connected to the bit line; and a voltage regulator. The page buffer comprises a latch including first and second inverters coupled between a latch node and an inverted latch node; and a pull-down NMOS transistor for tripping the sensing result of the selected memory cell to the latch node. The voltage regulator adjusts a trip voltage by providing the source voltage to the pull-down NMOS transistor. The flash memory device reduce a trip voltage variation range by using only the pull-down NMOS transistor characteristics. Also, an OFF cell margin and an ON cell margin may be secured by adjusting the level of the trip voltage using the source voltage.

Growing community of inventors

Suwon-si, South Korea

Tae-Hong Kwon