Samsung Electronics Co., Ltd.

Tae-hong Kwon

Bilal Ahmad Janjua

Vivek Venkata Kalluru

Young-sun Min

Sung-whan Seo

Ki-won Kim

Chan Kim

Won-Taeck Jung

Dae Seok Byeon

Jin-Young Chun

Chi Weon Yoon

Ohsuk Kwon

Doogon Kim

Taeyun Lee

Chaehoon Kim

Kyoman Kang

Kyung Hwa Yun

Tae-Min Park

In order to permit dense integration of a high number of stacked word lines in the semiconductor memory device, a charge pump is included in the semiconductor memory device. The charge pump makes use of a capacitor. The capacitor is implemented with respect to the dense integration. Some components are placed under the stacked word lines, and some are not under the stacked word lines. The capacity of the capacitor not under the stacked word lines is provided in part by a parallel structure.

Semiconductor memory device with a plurality of amplification stages

A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.

Charge pump and memory device including the same

Methods of operating a memory device include at least partially charging a sensing node within a page buffer of the memory device to a first precharge voltage, by sampling a trip voltage of a sensing latch within the page buffer. Thereafter, a voltage of the sensing node is boosted from the first precharge voltage to a higher second precharge voltage. Then, a voltage of the sensing node that reflects a value of data stored in a memory cell of the memory device is developed at the sensing node. The developed voltage is then transferred to the sensing latch so that data stored by the sensing latch reflects the value of data stored in the memory cell.

Memory devices that sample latch trip voltages prior to reading data into latches and methods of operating same

An operating method of a nonvolatile memory device includes determining whether a memory block is a selected block, and when the memory block is not the selected block, determining whether the memory block shares a block word line with the selected block. The method further includes applying an unselected block word line voltage to word lines of the memory block when the memory block shares the block word line with the selected block, and floating the word lines of the memory block when the memory block does not share the block word line with the selected block.

Nonvolatile memory device, storage device having the same, operating method thereof

A nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a CSL driver, and control logic. The memory cell array includes a plurality of memory blocks each having a plurality of strings that are formed in a direction perpendicular to a substrate and are connected between bit lines and a common source line. The CSL driver sets up the common source line with a predetermined voltage and supplies or drains charge to or from the common source line using a voltage level of the common source line as a feedback signal.

Nonvolatile memory device and programming method thereof including common source line feedback during program and verification operation

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Seoul, South Korea

Tae-hong Kwon