Applied Materials, Inc.

Tae Hong Ha

Xianmin Tang

Feng Chen

Lu Chen

Wenjing Xu

Yu Lei

Zhiyuan Wu

Gang Shen

Xiangjin Xie

Sang-Hyeob Lee

Wei Lei

Xuesong Lu

Yufei Hu

Jin Hee Park

Tza-Jing Gung

Yi Xu

Raymond Hoiman Hung

Rui Li

Andrew Nguyen

Er-Xuan Ping

Philip Allan Kraus

Avgerinos V Gelatos

Joung Joo Lee

Jaesoo Ahn

Thomas Jongwan Kwon

Takashi Kuratomi

Shirish A Pethe

Chung Liu

Hui Sun

Carmen Leal Cervantes

Mark Hyun Lee

Sree Rangasai Kesapragada

Chris Pabelico

Szuheng Ho

Mei Yin Chang

Mehul B Naik

Feng Quan Liu

Paul F Ma

Sang Ho Yu

Fuhong Zhang

Kevin Kashefi

Rong Tao

Ben-Li Sheu

Cheng-Hsiung Matthew Tsai

Srinivas Guggilla

Alexander Jansen

Lanlan Zhong

Aravind Kamath

Winsor Lam

Kiejin Park

Kie Jin Park

Yizhak Sabba

Christina L Engler

Ge Qu

Yong Jin Kim

Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHFgases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH—NFplasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.

Directional selective junction clean with field polymer protections

Methods for producing a reduced contact resistance for cobalt-titanium structures. In some embodiments, a method comprises depositing a titanium layer using a chemical vapor deposition (CVD) process, depositing a first cobalt layer on the titanium nitride layer using a physical vapor deposition (PVD) process, and depositing a second cobalt layer on the first cobalt layer using a CVD process.

Methods for controlling contact resistance in cobalt-titanium structures

Methods of forming copper interconnects are described. A doped tantalum nitride layer formed on a copper layer on a substrate has a first amount of dopant. The doped tantalum nitride layer is exposed to a plasma comprising one or more of helium or neon to form a treated doped tantalum nitride layer with a decreased amount of dopant. Apparatus for performing the methods are also described.

Impurity removal in doped ALD tantalum nitride

Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.

Method of forming a metal liner for interconnect structures

Methods for selective deposition are described herein. Further, methods for improving selectivity comprising an ammonia plasma pre-clean process are also described. In some embodiments, a silyl amine is used to selectively form a surfactant layer on a dielectric surface. A ruthenium film may then be selectively deposited on a conductive surface. In some embodiments, the ammonia plasma removes oxide contaminations from conductive surfaces without adversely affecting the dielectric surface.

Methods of selective deposition

Apparatuses and methods to provide electronic devices having metal films are provided. Some embodiments of the disclosure utilize a metallic tungsten layer as a liner that is filled with a metal film comprising cobalt. The metallic tungsten layer has good adhesion to the cobalt leading to enhanced cobalt gap-fill performance.

Deposition of metal films with tungsten liner

Methods and apparatus for processing a substrate include cleaning and self-assembly monolayer (SAM) formation for subsequent reverse selective atomic layer deposition. An apparatus may include a process chamber with a processing volume and a substrate support including a pedestal, a remote plasma source fluidly coupled to the process chamber and configured to produce radicals or ionized gas mixture with radicals that flow into the processing volume to remove residue or oxides from a surface of the substrate, a first gas delivery system with a first ampoule configured to provide at least one first chemical into the processing volume to produce a SAM on the surface of the substrate, a heating system located in the pedestal and configured to heat a substrate by flowing gas on a backside of the substrate, and a vacuum system fluidly coupled to the process chamber and configured to control heating of the substrate.

Methods and apparatus for precleaning and treating wafer surfaces

Electronic devices and methods of forming electronic devices using a ruthenium or doped ruthenium liner and cap layer are described. A liner with a ruthenium layer and a cobalt layer is formed on a barrier layer. A conductive fill forms a second conductive line in contact with the first conductive line.

Ruthenium liner and cap for back-end-of-line

Ruthenium liner and cap for back-end-of-line applications

Described are microelectronic devices comprising a dielectric layer formed on a substrate, a feature comprising a gap defined in the dielectric layer, a barrier layer on the dielectric layer, a two metal liner film on the barrier layer and a gap fill metal on the two metal liner. Embodiments provide a method of forming a microelectronic device comprising the two metal liner film on the barrier layer.

Binary metal liner layers

Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHFgases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH&#x2014;NFplasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are&#x2014;etched only minimally or not at all.

Methods and apparatus for filling features on a substrate are provided herein. In some embodiments, a method of filling features on a substrate includes: depositing a first metallic material on the substrate and within a feature disposed in the substrate in a first process chamber via a chemical vapor deposition (CVD) process at a first temperature; depositing a second metallic material on the first metallic material in a second process chamber at a second temperature and at a first bias power to form a seed layer of the second metallic material; etching the seed layer in the second process chamber at a second bias power greater than the first bias power to form an intermix layer within the feature comprising the first metallic material and the second metallic material; and heating the substrate to a third temperature greater than the second temperature, causing a reflow of the second metallic material.

Methods and apparatus for intermixing layer for enhanced metal reflow

Methods and apparatus for producing a reduced contact resistance for cobalt-titanium structures. In some embodiments, a method comprises depositing a titanium layer using a chemical vapor deposition (CVD) process, depositing a titanium nitride layer on the titanium layer using an atomic layer deposition (ALD) process, depositing a first cobalt layer on the titanium nitride layer using a physical vapor deposition (PVD) process, and depositing a second cobalt layer on the first cobalt layer using a CVD process.

Methods and apparatus for controlling contact resistance in cobalt-titanium structures

Methods and apparatus for selectively depositing a tungsten layer atop a dielectric surface. In embodiments the method includes: depositing a tungsten layer via a physical vapor deposition (PVD) process atop a substrate field and atop a sidewall and a dielectric bottom surface of a feature disposed in a substrate to form a first tungsten portion having a first thickness atop the substrate field, a second tungsten portion having a second thickness atop the sidewall, and a third tungsten portion having a third thickness atop the dielectric bottom surface, wherein the second thickness is less than the first thickness and third thickness; oxidizing a top surface of the tungsten layer to form a first oxidized tungsten portion atop the substrate field, a second oxidized tungsten portion atop the side wall, and a third oxidized tungsten portion atop the dielectric bottom surface; removing the first oxidized tungsten portion, the second oxidized tungsten portion and the third oxidized tungsten portion, wherein the second tungsten portion is completely removed from the sidewall; and passivating or completely removing the first tungsten portion from the substrate field.

Methods for selective deposition of tungsten atop a dielectric layer for bottom up gapfill

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San Jose, CA, United States of America

Tae Hong Ha