Hynix Semiconductor Inc.

Hyundai Electronics Industries Co. Ltd.

Tae Ho Cha

Se Aug Jang

Tae Kyun Kim

In Seok Yeo

Dae Gyu Park

Heung Jae Cho

Kwan Yong Lim

Jin Won Park

Jeong Youb Lee

Jin Sang Park

Dea Gyu Park

A method of forming dual-metal gates in a semiconductor device, including the steps of providing a semiconductor substrate having a PMOS area and an NMOS area wherein dummy gates are formed in the PMOS and NMOS areas respectively, forming an insulating interlayer on the semiconductor substrate so as to cover the dummy gates, polishing the insulating interlayer until the dummy gates are exposed, forming a first groove defining a first metal gate area by selectively removing one of the dummy gates formed in the PMOS and NMOS areas, forming a first gate insulating layer and a first metal layer on an entire area of the semiconductor substrate including the first groove successively, forming a first metal gate in the first groove by etching the first metal layer and first gate insulating layer until the insulating interlayer is exposed, forming a second groove defining a second metal gate area by removing the remaining dummy gate, forming a second gate insulating layer and a second metal layer on the entire area of the semiconductor substrate including the second groove, and forming a second metal gate in the second groove by etching the second metal layer and second gate insulating layer until the insulating interlayer is exposed.

Method of forming dual-metal gates in semiconductor device

There is disclosed a method of manufacturing a transistor in a semiconductor device. The present invention forms a Ta film or a TaNx film at a low temperature or forms a first TaNx film in which the composition(x) of nitrogen is 0.45&tilde;0.55, on a gate insulating film in a NMOS region, so that the work function becomes 4.0&tilde;4.4 eV, and also forms a Ta film or a TaNx film at a high temperature or forms a second TaNx film in which the composition(x) of nitrogen is 0.6&tilde;1.4 is formed, on a gate insulating film in a PMOS region, so that the work function becomes 4.8&tilde;5.2 eV. Thus, the present invention can lower the threshold voltage by implementing a surface channel CMOS device both in the NMOS region and the PMOS region.

Method of manufacturing a transistor in a semiconductor device

A method for fabricating a dual metal gate structure for a semiconductor device including deposition of a semiconductor substrate having PMOS and NMOS regions, a first gate having a first insulating layer and a first metal layer is formed in a first region. The first region is either the PMOS or NMOS region, and the remaining region becomes a second region. A dummy gate is formed in the second region. A spacer and a source/drain region are formed for each of the first and dummy gates. The dummy gate, however, is removed to expose a portion of the substrate in the second region. A second gate constructed of a second gate insulating layer and a second metal layer is then formed on the exposed portion of the substrate in the second region.

Method for fabricating a dual metal gate for a semiconductor device

There is disclosed a method of forming a gate electrode in a semiconductor device. The present invention forms a gate insulating film using (TiO ) (Al O ) in which a titanium oxide film (TiO ) having a high dielectric constant and an aluminum oxide film having leakage and interfacial property are mixed. Therefore, the present invention could not only improve the leakage current characteristic of a semiconductor device but also early develop a high-speed device having a high density in the future.

Method of forming a gate electrode in a semiconductor device

A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (Ti Al ) N film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (Ti Al ) N film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.

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Kyoungki-do, South Korea

Tae Ho Cha