Samsung Electronics Co., Ltd.

Tae-heon Kim

Tae-hyun Kim

Jin-kyu Park

Jong-won Kim

Jae-pil Shin

Yong-hyeon Kim

Patterns in an integrated circuit may be evaluated, and a semiconductor device may be fabricated based on the evaluation. The evaluation may include a extracting and superimposing first patterns corresponding to design patterns of the same shape from input layout data generated based on inspecting the integrated circuit, generating distribution data of the first patterns based on the superimposed first patterns, determining an evaluation contour of the design patterns based on an evaluation condition and the distribution data, and generating output layout data based on replacing the first patterns with second patterns each having the evaluation contour. Weak points in the integrated circuit may be detected based on the output layout data. The fabricating may include selectively incorporating an integrated circuit into a semiconductor device based on a determination that the integrated circuit includes less than a threshold quantity and/or threshold concentration of weak points.

Systems and methods of fabricating semiconductor devices

A method of forming contact plugs of a semiconductor device is provided. Bit lines are formed over a semiconductor substrate in which a predetermined lower layer is formed and a cell area and a core area are defined. An interlayer dielectric layer is formed over the semiconductor substrate over which the bit lines are formed. The interlayer dielectric layer is wet etched until the interlayer dielectric layer is recessed from the upper surfaces of the bit lines to a predetermined depth. A dielectric layer for forming spacers is formed over the semiconductor substrate, the dielectric layer having a step difference formed due to the wet etching of the interlayer dielectric layer. The dielectric layer in the core area is left and the dielectric layer in the cell area is etched by an anisotropic method to form spacers of the dielectric layer in the cell area. The interlayer dielectric layer is etched using the spacers and the dielectric layer as a mask to form contact holes. A conductive layer is deposited over the semiconductor substrate where the contact holes are formed to fill the contact holes.

Growing community of inventors

Hwaseong-si, South Korea

Tae-heon Kim