Hynix Semiconductor Inc.

Skhynix Inc.

Tae-Han Kim

Mi-Ri Lee

Su-Ho Kim

Yong-Seok Eun

Kyong-Bong Rouh

Shang-Koon Na

Dong-Hyun Kim

Ki-Won Nam

A method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer; forming an undercut prevention layer between the silicon containing layer and the metal containing layer; etching the metal-containing layer; and forming a conductive structure by etching the undercut prevention layer and the silicon-containing layer.

Method for fabricating semiconductor device including silicon-containing layer and metal-containing layer, and conductive structure of the same

A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, sequentially forming a silicon layer and a metal layer over the gate insulation layer, performing a first gate etching process to etch the metal layer using a gate hard mask layer, formed on the metal layer, as an etch barrier, and then partially etch the silicon layer, thereby forming a first pattern, performing a second gate etching process to partially etch the silicon layer, thereby forming an undercut beneath the metal layer, forming a capping layer on both sidewalls of the first pattern including the undercut, performing a third gate etching process to etch the silicon layer to expose the gate insulation layer using the gate hard mask layer and the capping layer as an etch barrier, thereby forming a second pattern, and performing a gate re-oxidation process.

Method for fabricating semiconductor device

A method for forming a pattern in a semiconductor device includes forming an etch target layer comprising metal over a substrate. A hard mask pattern is formed over the etch target layer. The etch target layer is etched to form a pattern such that a line width of the etch target layer is smaller than a line width of the hard mask pattern.

Method for forming pattern in semiconductor device

A method for fabricating a semiconductor device includes forming a polysilicon layer, a barrier metal layer, and a conductive layer over a substrate, forming gate hard masks over the conductive layer, etching the conductive layer and the barrier metal layer using the gate hard masks to form barrier metal electrodes and metal gate electrodes having a line width smaller than that of the gate hard masks, etching the polysilicon layer to form gate patterns, each gate pattern including a stack structure of a polysilicon electrode, the barrier metal electrode, the metal gate electrode, and the gate hard mask, forming a gate spacer over the surface profile of the substrate structure, forming an insulation layer over the gate spacer, etching the insulation layer to form a contact hole between the gate patterns and burying a conductive material over the contact hole to form a landing plug contact.

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Gyeonggi-do, South Korea

Tae-Han Kim